參數(shù)資料
型號(hào)： Eval-AD1940EB
廠商： Analog Devices, Inc.
英文描述： SigmaDSP-TM Multichannel 28-Bit Audio Processor
中文描述： SigmaDSP的，商標(biāo)多通道28位音頻處理器
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 478K
代理商： EVAL-AD1940EB
AD1940
INITIALIZATION
POWER-UP SEQUENCE
The AD1940 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the
contents of the internal program boot ROM are copied to the
internal program RAM memory, and the parameter RAM
(all 0s) is filled with values from its associated boot ROM. The
default boot ROM program simply copies the serial inputs to
the serial outputs with no processing. The data memories are
also cleared during this time.
Rev. 0 | Page 29 of 32
The boot sequence, which starts on the rising edge of the
RESETB pin, lasts for 8,192 cycles of the signal on the MCLK
pin at start-up. Assuming even the slowest possible signal on
this pin, a 64 × f
S
clock, the boot sequence will still complete
before the PLL locks to the input clock. Since the boot sequence
requires a stable master clock, the user should avoid writing to
or reading from the registers until the MCLK input signal has
settled and the PLL has locked. The PLL takes approximately
3 ms to lock. Coming out of reset, the clock mode is imme-
diately set by the PLL_CTRL0, PLL_CTRL1, and PLL_CTRL2
pins. Reset is synched to the falling edge of the internal MCLK.
The power-up default signal processing flow in the AD1940
simply takes the eight inputs and copies these signals to the
16 digital outputs, as shown in Figure 21.
0
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
Figure 21. Default Program Signal Flow
SETTING MASTER CLOCK/PLL MODE
The AD1940’s MCLK input feeds a PLL, which generates the
1536 × f
S
clock to run the DSP core. In normal operation, the
input to MCLK must be one of the following; 64 × f
S
, 256 × f
S
,
384 × f
S
, or 512 × f
S
, where f
S
is the input sampling rate. The
mode is set on PLL_CTRL0, PLL_CTRL1, and PLL_CTRL2,
according to Table 36. If the AD1940 is set to receive double-
rate signals (by reducing the number of program steps/sample
by a factor of 2 using the core control register), then the master
clock frequencies must be either 32 × f
S
, 128 × f
S
, 192 × f
S
, or
256 × f
S
. If the AD1940 is set to receive quad-rate signals (by
reducing the number of program steps/sample by a factor of 4
using the core control register), then the master clock
frequencies must be one of 16 × f
S
, 64 × f
S
, 96 × f
S
, or 128 × f
S
.
On power-up, a clock signal must be present on MCLK so that
the AD1940 can complete its initialization routine. The PLL can
also run in bypass mode, where the clock present on MCLK is
fed directly to the DSP core, although this setting is not
recommended for normal operation.
Table 36. PLL Modes
MCLK Input
PLL_CTRL2
64 × f
S
0
256 × f
S
0
384 × f
S
X
1
512 × f
S
1
Bypass
1
PLL_CTRL1
0
1
X
1
0
1
PLL_CTRL0
0
0
1
0
0
1
X = don’t care
The clock mode should not be changed without also resetting
the AD1940. If the mode is changed on the fly, a click or pop
may result on the outputs. The state of the PLL_CTRLx pins
should be changed while RESETB is held low.
VOLTAGE REGULATOR
The AD1940 includes an on-board voltage regulator that allows
the chip to be used in systems where a 2.5 V supply is not
available, but 3.3 V or 5 V is. The only external components
needed for this are a PNP transistor such as an FZT953, a single
capacitor, and a single resistor. The recommended design for the
voltage regulator is shown in Figure 22. The 10 μF and 100 nF
capacitors shown in this schematic are recommended for
bypassing, but are not necessary for operation. Here, VDD is the
main system voltage (3.3 V or 5 V) and should be connected to
VSUPPLY. 2.5 V is generated at the transistor’s collector, which
is connected to the VDD pins, PLL_VDD and VSENSE. The
reference voltage on VREF is 1.15 V and is generated by the
regulator. A 1 nF capacitor should be connected between this
pin and ground. VDRIVE is connected to the base of the PNP
transistor. A 1 k resistor should be connected between
VDRIVE and VSUPPLY.
If the regulator is not used in the design, VSUPPLY, VREF,
VDRIVE, and VSENSE can be tied to ground.
10
μ
F
10
μ
F
100nF
100nF
1nF
1k
AD1940
DVDD
FZT953
0
V
V
V
V
V
+
+
P
Figure 22. Voltage Regulator Design
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1940MINIB 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述:
EVAL-AD1940MINIBZ 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
EVAL-AD1941EB 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk
EVAL-AD1953EB 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS))
EVAL-AD1953EBZ 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk
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