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參數(shù)資料
| 型號： | EVAL-AD1953EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 13/36頁 |
| 文件大小： | 750K |
| 代理商： | EVAL-AD1953EB |
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REV. 0
AD1953
–13–
Each section of this flow diagram will be explained in detail on
the following pages.
Numeric Formats
It is common in DSP systems to use a standardized method of
specifying numeric formats. To better comprehend issues relat-
ing to precision and overflow, it is helpful to think in terms of
fractional twos complement number systems. Fractional
number systems are specified by an A.B format, where A is the
number of bits to the left of the decimal point and B is the
number of bits to the right of the decimal point. In a twos
complement system, there is also an implied offset of one-half of
the binary range; for example, in a twos complement 1.23 sys-
tem, the legal signal range is –1.0 to (+1.0 – 1 LSB).
The AD1953 uses two different numeric formats; one for the
coefficient values (stored in the parameter RAM) and one for
the signal data values. The coefficient format is as follows:
Coefficient Format
Coefficient format: 2.20
Range: –2.0 to (+2.0 – 1 LSB)
Examples:
1000000000000000000000 = –2.0
1100000000000000000000 = –1.0
1111111111111111111111 = (1 LSB below 0.0)
0000000000000000000000 = 0.0
0100000000000000000000 = 1.0
0111111111111111111111 = (2.0 – 1 LSB)
This format is used because standard biquad filters require
coefficients that range between +2.0 and –2.0. It also allows
gain to be inserted at various places in the signal path.
Internal DSP Signal Data Format
Input data format: 1.23
This is sign-extended when written to the data memory of the
AD1953.
Internal DSP signal data format: 3.23
Range: –4.0 to (+4.0 – 1 LSB)
Examples:
10000000000000000000000000 = –4.0
11000000000000000000000000 = –2.0
11100000000000000000000000 = –1.0
11111111111111111111111111 = (1 LSB below 0.0)
00000000000000000000000000 = 0.0
00100000000000000000000000 = 1.0
01000000000000000000000000 = 2.0
01111111111111111111111111 = (4.0 – 1 LSB).
The sign-extension between the serial port and the DSP core
allows for up to 12 dB of gain in the signal path without internal
clipping. Gains greater than 12 dB can be accommodated by
scaling the input down in the first biquad filter, and scaling the
signal back up at the end of the biquad filter section.
A digital clipper circuit is used between the output of the DSP
core and the input to the DAC
Σ
-
modulators to prevent over-
loading the DAC circuitry (see Figure 4). Note that there is a
gain factor of 0.75 used in the DAC interpolation filters, and
therefore signal values of up to 1/0.75 will pass through the DSP
without clipping. Since the DAC is designed to produce an
analog output of 2 V rms (differential) with a 0 dB digital input,
signals between 0 dB and 1/0.75 (approximately 3 dB) will produce
larger analog outputs and result in slightly degraded analog per-
formance. This extra analog range is necessary in order to pass 0
dBFS square waves through the system, as these square waves
cause overshoots in the interpolation filters that would otherwise
briefly clip the digital DAC circuitry.
A separate digital clipper circuit is used in the DSP core to
ensure that any accumulator values that exceed the numeric
3.23 format range are clipped when taken from the accumulator.
High-Pass Filter
The high-pass filter is a first-order double-precision design. The
purpose of the high-pass filter is to remove digital dc from the
input. If this dc were allowed to pass, the detectors used in the
compressor/limiter would give an incorrect reading for low
signal levels.
The high-pass filter is controlled by a single parameter
(alpha_HPF), which is programmed by writing to SPI location
180 in 2.20 twos complement format. The following equation
can be used to calculate the parameter
Alpha_HPF
from the –3 dB
point of the filter:
where
EXP
is the exponential operator,
HPF_CUTOFF
is the
high-pass cutoff in Hz, and
f
S
is the audio sampling rate.
The default value for the –3 dB cutoff of the high-pass filter is
2.75 Hz at a sampling rate of 44.1 kHz.
Alpha HPF
_
EXP
HPF CUTOFF
f
S
1. –
–2 0
_
=
×
×
π
b0
IN
OUT
b1
b2
a1
a2
Z
–1
Z
–1
Z
–1
Z
–1
Figure 5. Biquad Filter
Biquad Filters
Each of the two input channels has seven second-order biquad
sections in the signal path. In addition, the left and right chan-
nels have two additional biquad filters that may be used either
as crossover filters or as additional equalization filters. The sub
channel has three additional biquad filters, also to be used as
equalization and/or crossover filters. In a typical scenario, the
SIGNAL PROCESSING
(3.23 FORMAT)
SERIAL PORT
DAC INTERPOLATION
FILTERS (3.23 FORMAT)
DIGITAL -
MODULATORS
(1.23 FORMAT)
DIGITAL
CLIPPER
DATA IN
2-BIT SIGN EXTENTION
0.75
1.23
3.23
Figure 4. Numeric Precision and Clipping Structure
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
| EVAL-AD1954EB | 制造商:Rochester Electronics LLC 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述: |
| EVAL-AD1955EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD1955 制造商:Analog Devices 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk |
| EVAL-AD1955EBZ | 功能描述:BOARD EVAL FOR AD1955 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| EVAL-AD1955EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD1955 STEREO DIGITAL AUDIO |
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