參數(shù)資料
型號： EVAL-AD1953EB
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號處理
英文描述： 16-bit fixed point DSP with Flash
中文描述： 具有閃存的 16 位定點(diǎn) DSP
文件頁數(shù)： 30/36頁
文件大?。?/td> 750K
代理商： EVAL-AD1953EB
REV. 0
AD1953
–30–
SERIAL DATA INPUT/OUTPUT PORTS
The AD1953’s flexible serial data input port accepts data in twos
complement, MSB first format. The left channel data field always
precedes the right channel data field. The serial mode is set by
using mode select bits in the SPI control register. In all modes
except for the right-justified mode, the serial port will accept an
arbitrary number of bits up to a limit of 24 (extra bits will not
cause an error, but they will be truncated internally). In the right-
justified mode, SPI control register bits are used to set the word
length to 16, 20, or 24 bits. The default on power-up is 24-bit mode.
Proper operation of the right-justified mode requires that there
be exactly 64 BCLK per audio frame.
Serial Data Input/Output Modes
Figure 19 shows the serial input modes. For the left-justified
mode, LRCLK is HIGH for the left channel, and LOW for the
right channel. Data is sampled on the rising edge of BCLK. The
MSB is left-justified to an LRCLK transition, with no MSB delay.
The left-justified mode can accept any word length up to 24 bits.
In I
2
S mode, LRCLK is low for the left channel and high for the
right channel. Data is valid on the rising edge of BCLK. The MSB
is left-justified to an LRCLK transition but with a single BCLK
period delay. The I
2
S mode can be used to accept any number
of bits up to 24.
In right-justified mode, LRCLK is high for the left channel and
low for the right channel. Data is sampled on the rising edge
of BCLK. The start of data is delayed from the LRCLK edge
by 16, 12, or 8 BCLK intervals, depending on the selected
word length. The default word length is 24 bits; other word
lengths are set by writing to Bits <1:0> of Control Register 1.
In right-justified mode, it is assumed that there are 64 BCLKs
per frame.
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
SDATA
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
NOTES
1. DSP MODE DOESN’T IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT
f
EXCEPT DSP MODE, WHICH IS 2
f
3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE
I
2
S MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
1/
f
S
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
Figure 19. Serial Input Modes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1953EBZ 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk
EVAL-AD1954EB 制造商:Rochester Electronics LLC 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:
EVAL-AD1955EB 制造商:Analog Devices 功能描述:Evaluation Board For AD1955 制造商:Analog Devices 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR 24 BIT 192KHZ DAC 120 DB - Bulk
EVAL-AD1955EBZ 功能描述:BOARD EVAL FOR AD1955 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD1955EBZ 制造商:Analog Devices 功能描述:EVAL BOARD, AD1955 STEREO DIGITAL AUDIO
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