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參數(shù)資料
| 型號： | EVAL-AD7694CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7694 |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標準）： | 6.3mW @ 250kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7694 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD7694ARMZRL7-ND - IC ADC 16BIT SAR 250KSPS 8-MSOP AD7694BRMZ-ND - IC ADC 16BIT SRL 250KSPS 8MSOP AD7694ARMZ-ND - IC ADC 16BIT SAR 250KSPS 8MSOP AD7694BRMZRL7-ND - IC ADC 16BIT SAR 250KSPS 8MSOP |
AD7694
Rev. A | Page 15 of 16
05003-
025
SDO
1 SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW.
D15
D14
D13
D1
D0
tDIS
SCK
1
2
3
14
15
161
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
CNV
CONVERSION
ACQUISITION
tCONV
tCYC
ACQUISITION
tACQ
tEN
Figure 24. Serial Interface Timing
DIGITAL INTERFACE
The AD7694 is compatible with SPI, QSPI, digital hosts, and
DSPs, for example, Blackfin ADSP-BF53x or ADSP-219x. The
connection diagram is shown in Figure 25 and the
corresponding timing diagram is shown in Figure 24.
A rising edge on CNV initiates a conversion and forces SDO to
high impedance. When the conversion is complete, the AD7694
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are clocked by SCK falling edges. The data is valid on both SCK
edges.
05003-024
CNV
SCK
SDO
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7694
Figure 25. Connection Diagram
LAYOUT
The printed circuit board that houses the AD7694 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7694 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7694 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7694s.
The AD7694 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7694 should be
decoupled with a ceramic capacitor, typically 100 nF. This
capacitor should be placed close to the AD7694 and connected
using short and large traces to provide low impedance paths
and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7694’S PERFORMANCE
Other recommended layouts for the AD7694 are outlined in the
evaluation board for the AD7694 (EVAL-AD7694). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD3.
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