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參數(shù)資料
| 型號(hào)： | EVAL-AD9831EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Complete DDS |
| 中文描述： | 完整的DDS的CMOS |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | EVAL-AD9831EB |
AD9831
–5–
REV. A
PIN DE SCRIPT ION
Mnemonic
Function
POWE R SUPPLY
AVDD
Positive power supply for the analog section. A 0.1
μ
F decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
Analog Ground.
Positive power supply for the digital section. A 0.1
μ
F decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V
±
10% or +3.3 V
±
10%.
Digital Ground.
AGND
DVDD
DGND
ANALOG SIGNAL AND RE FE RE NCE
IOUT
Current Output. T his is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. T his determines the
magnitude of the full-scale DAC current. T he relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
= 12.5
×
V
REFIN
/
R
SET
V
REFIN
= 1.21
V nominal
,
R
SET
= 3.9 k
typical
REFIN
Voltage Reference Input. T he AD9831 can be used with either the on-board reference, which is available from pin
REFOUT , or an external reference. T he reference to be used is connected to the REFIN pin. T he AD9831
accepts a reference of 1.21 V nominal.
REFOUT
Voltage Reference Output. T he AD9831 has an on-board reference of value 1.21 V nominal. T he reference is
made available on the REFOUT pin. T his reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGIT AL INT E RFACE AND CONT ROL
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK . T he
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one
MCLK cycle as to when control is transferred to the other frequency register. T o avoid any uncertainty, a change
on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-T riggered Digital Input. T he
WR
pin is used when writing data to the AD9831. T he data is loaded
into the AD9831 on the rising edge of the
WR
pulse. T his data is then loaded into the destination register on the
MCLK rising edge. T he
WR
pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. T he
WR
rising
edge should occur before an MCLK rising edge. T he data will then be loaded into the destination register on the
MCLK rising edge. Alternatively, the
WR
rising edge can occur after the MCLK rising edge and the destination
register will be loaded on the next MCLK rising edge.
D0–D15
Data Bus, Digital Inputs for destination registers.
A0–A2
Address Digital Inputs. T hese address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. T he AD9831 has four phase registers. T hese registers can be used to alter the value being
input to the SIN ROM. T he contents of the phase register can be added to the phase accumulator output, the
inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. T herefore, these inputs need to be in steady state when an MCLK rising
edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase
register.
SLEEP
Low Power Control, active low digital input.
SLEEP
puts the AD9831 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. T he AD9831 is re-enabled by taking
SLEEP
high.
RESET
Reset, active low digital input.
RESET
resets the phase accumulator to zero which corresponds to an analog
output of midscale.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD9831EBZ | 功能描述:BOARD EVALUATION AD9831 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD9832EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk 制造商:Analog Devices 功能描述:AD9832 EVAL BOARD |
| EVAL-AD9832SDZ | 功能描述:BOARD EVAL FOR AD9832 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-AD9833EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| EVAL-AD9833EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For IC Programmable Waveform Generator 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR - Bulk |
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