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參數(shù)資料
| 型號： | EVAL-ADE7763EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Phase Active and Apparent Energy Metering IC |
| 中文描述： | 單相有功功率和視在電能計(jì)量IC |
| 文件頁數(shù)： | 5/56頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | EVAL-ADE7763EB |
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ADE7763
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T
MIN
to T
MAX
= 40°C to +85°C.
Table 2. Timing Characteristics
1, 2
Parameter
Spec
Unit
Write Timing
t
1
50
ns min
t
2
50
ns min
t
3
50
ns min
t
4
10
ns min
t
5
5
ns min
t
6
400
ns min
t
7
50
ns min
t
8
100
ns min)
Read Timing
t
93
4
μs min
Rev. A | Page 5 of 56
Test Conditions/Comments
CS falling edge to first SCLK falling edge.
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
Minimum time between read command (i.e., a write to
communication register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
communication register.
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
t
10
t
11
50
30
ns min
ns min
t
124
t
135
100
10
100
10
ns max
ns min
ns max
ns min
________________________________________________
1
Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
2
See Figure 3, Figure 4, and the Serial Interface section.
3
Minimum time between read command and data read for all registers except waveform register, which is t
9
= 500 ns min.
4
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
DIN
SCLK
CS
t
2
t
3
t
1
t
4
t
5
t
7
t
6
t
8
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
1
0
A4
A5
A3
A2
A1
A0
DB7
DB0
DB7
DB0
t
7
0
Figure 3. Serial Write Timing
SCLK
CS
t
1
t
10
t
13
0
0
A4
A5
A3
A2
A1
A0
DB0
DB7
DB0
DB7
DIN
DOUT
t
11
t
11
t
12
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
t
9
0
Figure 4. Serial Read Timing
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