參數(shù)資料
型號: EVAL-ADF4360-6EB1
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: Integrated Synthesizer and VCO
中文描述: 綜合合成器和VCO
文件頁數(shù): 11/24頁
文件大?。?/td> 487K
代理商: EVAL-ADF4360-6EB1
ADF4360-6
After band selection, normal PLL action resumes. The nominal
value of K
V
is 32 MHz/V or 16 MHz/V if divide-by-2 operation has
been selected (by programming DIV2 (DB22) high in the N
counter latch). The ADF4360 family contains linearization circuitry
to minimize any variation of the product of I
CP
and K
V
.
Rev. 0 | Page 11 of 24
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
VCO
RF
OUT
A
RF
OUT
B
BUFFER/
DIVIDE BY 2
0
OUTPUT STAGE
The RF
OUT
A and RF
OUT
B pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of 13.5 dBm, 10.5 dBm,
7.5 dBm, and 4.5 dBm, respectively, using a 50 resistor to
V
DD
and ac coupling into a 50 load. Alternatively, both out-
puts can be combined in a 1 + 1:1 transformer or a 180° micro-
strip coupler (see the Output Matching section).
Figure 15. Output Stage ADF4360-6
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EVAL-ADF4360-8EB1 Integrated Synthesizer and VCO
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相關(guān)代理商/技術(shù)參數(shù)
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