參數(shù)資料
型號: EVAL-ADF4360-8EB1
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: Integrated Synthesizer and VCO
中文描述: 綜合合成器和VCO
文件頁數(shù): 19/24頁
文件大?。?/td> 434K
代理商: EVAL-ADF4360-8EB1
ADF4360-8
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-8 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 21 shows a graph of both minimum
and maximum frequency versus the external inductor value.
The correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
Rev. 0 | Page 19 of 24
The lowest center frequency of oscillation possible is approxi-
mately 65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
(
)
EXT
O
L
F
+
=
nH
0.9
pF
9.3
1
0
150
50
100
350
250
300
200
450
400
0
100
200
300
400
600
500
INDUCTANCE (nH)
F
0
Figure 21. Output Center Frequency vs. External Inductor Value
Where
F
O
is the center frequency and
L
EXT
is the external induc-
tance. The approximate value of capacitance at the midpoint of
the center band of the VCO is 9.3 pF, and the approximate value
of internal inductance due to the bond wires is 0.9 nH. The
VCO sensitivity is a measure of the frequency change versus the
tuning voltage. It is a very important parameter for the low-pass
filter. Figure 22 shows a graph of the tuning sensitivity (in
MHz/V) versus the inductance (nH). It can be seen that as the
inductance increases, the sensitivity decreases. This relationship
can be derived from the equation above, i.e., since the induc-
tance has increased, the change in capacitance from the varactor
has less of an effect on the frequency.
0
4
2
10
8
6
12
0
100
200
300
400
600
500
INDUCTANCE (nH)
S
0
Figure 22. Tuning Sensitivity (in MHz/V) vs. Inductance (nH)
FIXED FREQUENCY LO
Figure 23 shows the ADF4360-8 used as a fixed frequency LO at
200 MHz. The low-pass filter was designed using ADIsimPLL
for a channel spacing of 2 MHz and an open-loop bandwidth of
100 kHz. The maximum PFD frequency of the ADF4360-8 is 8
MHz. Since using a larger PFD frequency allows the use of a
smaller N, the in-band phase noise is reduced to as low as
possible, 109 dBc/Hz. The typical rms phase noise (100 Hz to
100 kHz) of the LO in this configuration is 0.09°. The reference
frequency is from a 16MHz TCXO from Fox; thus, an R value of
2 is programmed. Taking into account the high PFD frequency
and its effect on the band select logic, the band select clock
divider is enabled. In this case, a value of 8 is chosen. A very
simple shunt inductor and dc blocking capacitor complete the RF
output stage.
S
ADF4360-8
V
VCO
C
N
V
VCO
FOX
801BE-160
16MHz
V
VCO
CPGND
AGND DGND L1 L2RF
OUT
B
11
22
15
RF
OUT
A
CP
1nF
47pF
68nH
470
68nH
470
22nF
56nH
56nH
680pF
51
100pF
100pF
1nF
1nF
10
μ
F
4.7k
6.8k
15k
R
SET
C
C
LE
DATA
CLK
REF
IN
V
TUNE
DV
DD
AV
DD
CE MUXOUT
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
3
8
9
10
12
V
VDD
LOCK
DETECT
0
Figure 23. Fixed Frequency LO
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