參數(shù)資料
型號(hào)： EVAL-ADF7012EB2
廠商： Analog Devices, Inc.
英文描述： Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter
中文描述： 多通道ISM頻段FSK信號(hào)/的GFSK /元件Ook /約克/ ASK發(fā)射
文件頁數(shù)： 16/28頁
文件大?。?/td> 772K
代理商： EVAL-ADF7012EB2
ADF7012
OUTPUT DIVIDER
An output divider is a programmable divider following the
VCO in the PLL loop. It is useful when using the ADF7012 to
generate frequencies of < 500 MHz.
Rev. 0 | Page 16 of 28
0
PFD
CP
PA
OUTPUT
DIVIDER
÷
1/2/4/8
LOOP
FILTER
REFERENCE
DIVIDER
÷
N
VCO
Figure 35. Output Divider Location in PLL.
The output divider may be used to reduce feedthrough of the
VCO by amplifying only the VCO/2 component, restricting the
VCO feedthrough to leakage.
Because the divider is in loop, the N register values should be
set up according to the usual formula. However, the VCO gain
(K
V
) should be scaled according to the divider setting, as shown
in the following example.
Fout = 433 MHz, Fvco = 866 MHz, K
V
@ 868 MHz =
60 MHz/V
Therefore, K
V
for loop filter design = 30 MHz/V.
The divider value is set in the R register.
Table 5.
OD1
0
0
1
1
MUXOUT MODES
The MUXOUT pin allows the user access to various internal
signals in the transmitter, and provides information on the
PLL lock status, the regulator, and the battery voltage. The
MUXOUT is accessed by programming Bits M1 to M4 in the
function register and observing the signal at the MUXOUT pin.
OD2
0
1
0
1
Divider Status
Divider off
Divide by 2
Divide by 4
Divide by 8
Battery Voltage Read back
By setting MUXOUT to 1010 to 1101, the battery voltage can be
estimated. The battery measuring circuit features a voltage
divider and a comparator where the divided-down supply
voltage is compared to the regulator voltage.
Table 6.
MUXOUT
MUXOUT High
1010
DV
DD
> 3.25 V
1011
DV
DD
> 3.0 V
1100
DV
DD
> 2.75 V
1101
DV
DD
> 2.35 V
MUXOUT Low
DV
DD
< 3.25 V
DV
DD
< 3.0 V
DV
DD
< 2.75 V
DV
DD
< 2.35 V
The accuracy of the measurement is limited by the accuracy of
the regulator voltage and also the internal resistor tolerances.
Regulator Ready
The regulator has a power-up time, dependant on process and
the external capacitor. The regulator ready signal indicates that
the regulator is fully powered, and that the serial interface is
active. This is the default setting on power-up at MUXOUT.
Digital Lock Detect
Digital lock detect indicates that the status of the PLL loop.
The PLL loop takes time to settle on power-up and when the
frequency of the loop is changed by changing the N value.
When lock detect is high, the PFD has counted a number of
consecutive cycles where the phase error is < 15 ns. The lock
detect precision bit in the function register determines whether
this is 3 cycles (LDP = 0), or 5 cycles (LDP=1). It is recom-
mended that LDP be set to 1. The lock detect is not completely
accurate and goes high before the output has settled to exactly
the correct frequency. In general, add 50% to the indicated
lock time to obtain lock time to within 1 kHz. The lock detect
signal can be used to decide when the power amplifier (PA)
should be enabled.
R Divider
MUXOUT provides the output of the R divider. This is a
narrow pulsed digital signal at frequency F
PFD
. This signal may
be used to check the operation of the crystal circuit and the R
divider. R divider/2 is a buffered version of this signal at F
PFD
/2.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADF7012EB3 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter
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EVAL-ADF7020-1DBZ5 功能描述:BOARD EVAL ADF7020-2 ADJ FREQ RoHS:是 類別:RF/IF 和 RFID >> RF 評(píng)估和開發(fā)套件，板 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關(guān)產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796
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