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ADM1026
Voltage Measurement Inputs
The internal structure for all the analog inputs is shown in
Figure 27. Each input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first-order low-
pass filter that gives each voltage measurement input immunity
to high frequency noise. The 12 V input also has a resistor
connected to the on-chip reference to offset the negative voltage
range so that it is always positive and can be handled by the
ADC. This allows most popular power supply voltages to be
monitored directly by the ADM1026 without requiring any
additional resistor scaling.
Rev. A | Page 18 of 56
109.4k
18.5pF
21.9k
+V
CCP
9.3pF
V
REF
17.5k
114.3k
–12V
49.5k
82.7k
4.5pF
V
BAT
*SEE TEXT
A
IN0
– A
IN5
(0V – 3V)
109.4k
4.6pF
21.9k
A
– A
(0V – 2.5V)
4.6pF
52.5k
50k
4.6pF
83.5k
+5V
21k
9.3pF
113.5k
+12V
MUX
0
Figure 27. Voltage Measurement Inputs
Setting Other Input Ranges
A
IN0
to A
IN9
can easily be scaled to voltages other than 2.5 V or
3 V. If the input voltage range is zero to some positive voltage, all
that is required is an input attenuator, as shown in Figure 28.
R1
R2
V
IN
A
IN(0–9)
0
Figure 28. Scaling A
IN0
A
IN9
However, when scaling A
IN0
to A
IN5
, it should be noted that
these inputs already have an on-chip attenuator, because their
primary function is to monitor SCSI termination voltages. This
attenuator loads any external attenuator. The input resistance of
the on-chip attenuator can be between 100 k and 200 k. For
this tolerance not to affect the accuracy, the output resistance
of the external attenuator should be very much lower than
this, that is, 1 k in order to add not more than 1% to the
total unadjusted error (TUE). Alternatively, the input can be
buffered using an op amp.
(
IN0
A
R2
0
(
IN6
A
R2
5
)
(
)
IN5
fs
A
V
R1
to
for
0
=
)
(
)
IN9
fs
A
V
R1
to
for
5
=
Negative and bipolar input ranges can be accommodated by
using a positive reference voltage to offset the input voltage
range so that it is always positive. To monitor a negative input
voltage, an attenuator can be used as shown in Figure 29.
R1
R2
V
IN
A
IN(0–9)
0
Figure 29. Scaling and Offsetting A
IN0
A
IN9
for Negative Inputs
This offsets the negative voltage so that the ADC always sees a
positive voltage. R1 and R2 are chosen so that the ADC input
voltage is zero when the negative input voltage is at its
maximum (most negative) value, that is:
OS
fs
V
V
R2
R1
=
This is a simple and low cost solution, but note the following:
Because the input signal is offset but not inverted, the input
range is transposed. An increase in the magnitude of the
negative voltage (going more negative) causes the input
voltage to fall and give a lower output code from the ADC.
Conversely, a decrease in the magnitude of the negative
voltage causes the ADC code to increase. The maximum
negative voltage corresponds to zero output from the ADC.
This means that the upper and lower limits are transposed.
For the ADC output to be full scale when the negative
voltage is zero, V
OS
must be greater than the full-scale
voltage of the ADC, because V
OS
is attenuated by R1 and
R2. If V
OS
is equal to or less than the full-scale voltage of
the ADC, the input range is bipolar but not necessarily
symmetrical.
This is a problem only if the ADC output must be full scale
when the negative voltage is zero.