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參數(shù)資料
| 型號： | EVAL-ADM1026EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete Thermal and System Management Controller |
| 中文描述： | 完整的熱和系統(tǒng)管理控制器 |
| 文件頁數(shù)： | 44/56頁 |
| 文件大?。?/td> | 634K |
| 代理商： | EVAL-ADM1026EB |
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ADM1026
Rev. A | Page 44 of 56
Table 42. Register 1Dh, Mask Register 6 (Power-On Default 00h)
Bit
Name
R/W
0
GPIO8 Mask = 0
R/W
1
GPIO9 Mask = 0
R/W
2
GPIO10 Mask = 0
R/W
3
GPIO11Mask = 0
R/W
4
GPIO12 Mask = 0
R/W
5
GPIO13 Mask = 0
R/W
6
GPIO14 Mask = 0
R/W
7
GPIO15 Mask = 0
R/W
Description
When this bit is set, interrupts generated on the
GPIO8 channel are masked out.
When this bit is set, interrupts generated on the
GPIO9 channel are masked out.
When this bit is set, interrupts generated on the
GPIO10 channel are masked out.
When this bit is set, interrupts generated on the
GPIO11 channel are masked out.
When this bit is set, interrupts generated on the
GPIO12 channel are masked out.
When this bit is set, interrupts generated on the
GPIO13 channel are masked out.
When this bit is set, interrupts generated on the
GPIO14 channel are masked out.
When this bit is set, interrupts generated on the
GPIO15 channel are masked out.
Table 43. Register 1Eh, INT Temp Offset (Power-On Default 00h)
Bit
Name
R/W
7–0
Int Temp Offset
R/W
Description
This register contains the offset value for the internal temperature channel, a twos complement
result before it is stored or compared to limits. In this way, a sort of one-point calibration can be
done whereby the whole transfer function of the channel can be moved up or down. From a
software point of view, this may be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change for any reason (for instance from one
chassis to another), if the measurement point is moved, if a plug-in card is inserted or removed, and
so on.
Table 44. Register 1Fh, INT Temp Measured Value (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
Int Temp Value
R
This register contains the measured value of the internal temperature channel.
Table 45. Register 20h, Status Register 1 (Power-On Default 00h)
Bit Name
R/W
0
Ext1 Temp Status = 0
R
Description
1, if Ext1 value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext1 temp readings
exceeding the Ext1 THERM limit. This bit is also set (once only) if THERM mode is disengaged as a
result of Ext1 temperature readings going 5°C below Ext1 THERM limit.
1, if Ext 2 value (or A
IN9
if in voltage measurement mode) is above the /A
IN9
status = 0 high limit or
below the low limit on the previous conversion cycle; 0 otherwise. This bit is set (once only) if a
THERM mode is engaged as a result of Ext2 temperature readings exceeding the Ext2 THERM limit.
This bit is also set (once only) if THERM mode is disengaged as a result of Ext2 temperature readings
going 5°C below Ext2 THERM limit.
1, if 3.3 V STBY value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
1, if 3.3 V MAIN value is above the high limit or below the low limit on the previous conversion
cycle; 0 otherwise.
1, if +5 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
1, if V
CCP
value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
1, if +12 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
1, if
12 V value is above the high limit or below the low limit on the previous conversion cycle;
0 otherwise.
1
Ext2 Temp Status = 0
R
2
3.3 V STBY Status = 0
R
3
3.3 V MAIN Status = 0 R
4
+5 V Status = 0
R
5
V
CCP
Status = 0
R
6
+12 V Status = 0
R
7
12 V Status = 0
R
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