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參數(shù)資料
| 型號： | EVAL-ADN2819-CML |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 限幅放大器 |
| 英文描述： | Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| 中文描述： | 多速率為2.7 Gb / s的集成時鐘和數(shù)據(jù)恢復(fù)芯片限幅放大器 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 570K |
| 代理商： | EVAL-ADN2819-CML |
ADN2819
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2819 must
be chosen such that the device works properly at the lower
OC-3 and higher OC-48 data rates. When choosing the
capacitors, the time constant formed with the two 50 resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can drop due to baseline wander (see Figure 23), causing
pattern dependent jitter (PDJ).
Rev. B | Page 19 of 24
For the ADN2819 to work robustly at both OC-3 and OC-48, a
minimum capacitor of 1.6 μF to PIN/NIN and 0.1 μF on
DATAOUTP/DATAOUTN should be used. This is based on the
assumption that 1000 CIDs must be tolerated and that the PDJ
should be limited to 0.01 UI p-p.
50
ADN2819
NIN
PIN
50
V
REF
C
IN
C
IN
V2
V1
V2b
V1b
TIA
LIMAMP
CDR
C
OUT
C
OUT
DATAOUTP
DATAOUTN
+
4
3
2
1
V1
V1b
V2
V2b
V
DIFF
V
DIFF
= V2–V2b
VTH = ADN2819 QUANTIZERTHRESHOLD
V
REF
VTH
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHENTHE OUTPUT OFTHE TIA GOESTO CID, V1 AND V1b ARE DRIVENTO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TOTHE V
REF
LEVEL,
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHENTHE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSSTHE AC COUPLING CAPACITORS IS APPLIEDTOTHE INPUT LEVELS,
CAUSING A DC SHIFT INTHE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCHTHAT ONE OFTHE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1bWHENTHE TIAWENTTO CID, IS CANCELLED OUT. THE QUANTIZERWILL NOT RECOGNIZETHIS AS AVALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTILTHE DIFFERENTIAL INPUTVOLTAGE EXCEEDSTHE SENSITIVITY OFTHE ADN2819.THE QUANTIZERWILL BE
ABLETO RECOGNIZE BOTH HIGH AND LOW STATES ATTHIS POINT.
0
Figure 25. Example of Baseline Wander
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