參數(shù)資料
型號(hào): EVAL-ADUC846QS
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: MicroConverter, Dual 16-Bit ADCs with Embedded 62kB FLASH MCU
中文描述: MicroConverter的,雙16的嵌入式62kB閃存MCU位ADC
文件頁數(shù): 11/20頁
文件大?。?/td> 1984K
代理商: EVAL-ADUC846QS
ADuC846
PRELIMINARY TECHNICAL DATA
Pin No:
52-MQFP
41
Pin No:
56-CSP
44
Pin
Mnemonic
PSEN
Type*
Description
Program Store Enable, Logic Output. This output is a control signal that
enables the external program memory to the bus during external fetch
operations. It is active every six oscillator periods except during external data
memory accesses. This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a
device power cycle.
Address Latch Enable, Logic Output. This output is used to latch the low byte
(and page byte for 24-bit data address space accesses) of the address to
external memory during external code or data memory access cycles. It is
activated every six oscillator periods except during an external data memory
access. It can be disabled by setting the PCON.4 bit in the PCON SFR.
P0.0–P0.7, these pins are part of Port0 which is an 8-bit open-drain
bidirectional I/O port. Port 0 pins that have 1s written to them float and in that
state can be used as high impedance inputs. An external pull-up resistor will
be required on P0 outputs to force a valid logic high level externally. Port 0 is
also the multiplexed low-order address and data bus during accesses to
external program or data memory. In this application it uses strong internal
pull-ups when emitting 1s.
42
45
ALE
43
46
49
52
46
49
52
55
P0.0
P0.7
I/O
*I = Input, O = Output, S = Supply.
REV. PrA
-11-
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