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參數(shù)資料
| 型號： | EVAL-ADV7189EBM |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | 標清多格式視頻解碼器 |
| 文件頁數(shù)： | 64/104頁 |
| 文件大小： | 890K |
| 代理商： | EVAL-ADV7189EBM |
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ADV7189
MPU PORT DESCRIPTION
The ADV7189 supports a 2-wire (I
2
C compatible) serial inter-
face. Four inputs, serial data (SDA1 and SDA2) and serial clock
(SCLK1 and SCLK2), carry information between the ADV7189
and the system I
2
C master controller. Each slave device is recog-
nized by a unique address. The ADV7189 has two ports: the
control port, which allows the user to set up and configure the
decoder; and the VBI data readback port, which allows the user
to read back captured VBI data. Both the control and VBI ports
have four possible slave addresses for both read and write oper-
ations, depending on the logic level on the ALSB pin. These four
unique addresses are shown in Table 170. The ADV7189’s ALSB
pin controls Bit 1 of the slave address. By altering the ALSB, it is
possible to control two ADV7189s in an application without
having a conflict with the same slave address. The LSB (Bit 0)
sets either a read or write operation. Logic 1 corresponds to a
read operation; Logic 0 corresponds to a write operation.
Table 170. I
2
C Address for ADV7189
Slave Address
Control Port
0
0
0x40
0
1
0x41
1
0
0x42
1
1
0x43
Rev. A | Page 64 of 104
ALSB
R/W
Slave Address
VBI Port
0x20
0x21
0x22
0x23
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establish-
ing a Start condition, which is defined by a high-to-low
transition on SDA1/SDA2 while SCLK1/SCLK2 remains high.
This indicates that an address/data stream will follow. All per-
ipherals respond to the Start condition and shift the next eight
bits (7-bit address + R/W bit). The bits are transferred from
MSB down to LSB. The peripheral that recognizes the trans-
mitted address responds by pulling the data line low during the
ninth clock pulse; this is known as an acknowledge bit. All other
devices withdraw from the bus at this point and maintain an
idle condition. The idle condition is where the device monitors
the SDA1/SDA2 and SCLK1/SCLK2 lines, waiting for the Start
condition and the correct transmitted address. The R/W bit
determines the direction of the data. Logic 0 on the LSB of the
first byte means the master will write information to the
peripheral. Logic 1 on the LSB of the first byte means the master
will read information from the peripheral.
The ADV7189 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. The ADV7189 has 196 subaddresses
to enable access to the internal registers. It therefore interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A
data transfer is always terminated by a Stop condition. The user
can also access any unique subaddress register on a one-by-one
basis without having to update all the registers.
Stop and Start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLK
high period, the user should only issue one Start condition, one
Stop condition, or a single Stop condition followed by a single
Start condition. If an invalid subaddress is issued by the user,
the ADV7189 will not issue an acknowledge and will return to
the idle condition.
If in auto-increment mode the user exceeds the highest
subaddress, the following action is taken:
1.
In read mode, the highest subaddress register contents
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDA line is not pulled
low on the ninth pulse.
2.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7189, and the part returns to the idle condition.
0
SDATA
SCLOCK
START ADDR
ACK
ACK
DATA
ACK
STOP
SUBADDRESS
1–7
1–7
8
9
8
9
1–7
8
9
S
P
R/W
Figure 36. Bus Data Transfer
0
S
WRITE
SEQUENCE
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S)
DATA
A(S)
P
S
READ
SEQUENCE
SLAVE ADDR
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
A(S)
DATA
A(M)
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
LSB = 1
LSB = 0
Figure 37. Read and Write Sequence
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