參數(shù)資料
型號(hào)： FMS7401LVN14
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： Digital Power Controller
中文描述： 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14
封裝： PLASTIC, DIP-14
文件頁(yè)數(shù)： 18/80頁(yè)
文件大?。?/td> 1535K
代理商： FMS7401LVN14
FMS7401/7401L
PRODUCT SPECIFICATION
18
REV. 1.0.2 6/23/04
Bit 6 of the ADCNTRL1 register is the ADC’s microcontroller hardware interrupt enabled (AINTEN) bit. If set, hardware
interrupts (ADCI) are enabled and triggered by the APND pending flag.
5
As long as the ADC pending flag is set, the hardware
interrupt will continue to execute software’s ADC interrupt service routine until the pending flag is cleared.
6
Bit 5 of the ADCNTRL1 register is the ADC Conversion Start/Busy (ASTART) bit. Software must set the ASTART bit to ini-
tiate an ADC conversion when the ENDAS bit of the ADCNTRL2 register is set to 0. The ASTART bit will remain high as long
as an ADC conversion is in progress (whether software or the ADSTROBE signal triggered the conversion). If software
attempts to clear the ASTART bit while a conversion is in progress, the write command is ignored and the ASTART bit remains
high until the conversion cycle completes. Software should monitor ASTART to determine when the conversion has completed
instead of the APND bit. The APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion
completion delay may occur when the F
ICLK
clock is slower than an ADC conversion clock cycle.
Bit 4 of the ADCNTRL1 register is the ADC Voltage Reference Selection (REFSEL) bit. If REFSEL=0, the ADC Reference
Voltage (V
AREF
) becomes sourced by the internal bandgap voltage reference (V
REF
). If REFSEL=1, the ADC Reference Voltage
(V
AREF
) becomes sourced by Vcc. If the ADC circuit is performing a conversion, software must avoid writing to the REFSEL
bit.
Bits 3-0 of the ADCNTRL1 register are the Analog Channel Selection (ACHSEL[3:0]) bits selecting one of the eight analog
input channels to convert its voltage (see
Table 6
). Software may write to the ACHSEL bits at any time; however, the actual
ACHSEL selection signals will not change while an ADC conversion is in progress. If a read command is issued while a con-
version is in progress, the current value of the ACHSEL bits may not necessarily reflect the actual state of the ACHSEL selec-
tion signals. The last value of the ACHSEL bits written by software at the time of the ADC conversion trigger, dictates the state
of the ACHSEL selection signals for the triggered ADC conversion cycle.
The SBIT or RBIT instructions may be used to either set or clear one of the ADCNTRL1 register bits, like the AINTEN bit.
The SBIT and RBIT instructions both take two instruction clock cycles to complete their execution. In the first cycle, all regis-
ter bits are automatically read to obtain their most current value. In the second cycle, the bit to be set/cleared is given its new
value and all bits are then re-written to the register. Using the SBIT/RBIT instruction to set/clear an enable bit with a pending
flag in the same register may cause a potential hazard. Software may inadvertently clear a recently triggered pending flag if the
trigger happened during the second phase of the SBIT/RBIT instruction execution. To avoid this condition, the LD instruction
must be used to set or clear the interrupt enable bit. The ADC circuit is designed such that software may not trigger a pending
flag by writing a 1 to the APND bit, it may only be cleared. The action of writing a 1 to the APND register bit holds its current
bit value. The action of writing a 0 to the APND register bit clears the bit value. Therefore, the “LD T1CNTRL, #0E0H”
instruction will set the ASTART and AINTEN bits without clearing APND.
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