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參數(shù)資料
| 型號(hào)： | FMS7401LVN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 30/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401LVN14 |
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FMS7401/7401L
PRODUCT SPECIFICATION
30
REV. 1.0.2 6/23/04
5.3
The Programmable Comparator’s output (C
OUT
) is fed into the digital delay filter with a programmable delay time. The C
OUT
signal toggles from 0 to 1 when the external input (G4/AIN0 or G2/AIN2) voltage is higher than the programmed voltage
threshold or Uncommitted Amplifier output (A
OUT
), depending on the state of VLOOP. The C
OUT
rising edge transition triggers
the programmable digital delay counter to begin incrementing. With each digital delay count, its value is compared against the
value stored in the DD[3:0] bits of the Digital Delay (DDELAY) control register. If C
OUT
remains high when the digital delay
count equaling DD[3:0] completes, the PWMOFF signal transitions from 0 to 1. This rising edge transition of the PWMOFF
signal is then used to either disable the PWM Timer 1 circuit completely or the current PWM cycle forcing the PWM output
signals to their resting (off) state. The PWMOFF output signal may also be programmed as an input of the G6 port MIW
circuit. Interrupts may be triggered if the G6 port MIW circuit is enabled and configured to trigger its microcontroller hardware
interrupt (EDGEI). Refer to the
Multi-input Wakeup Circuit
section of the datasheet regarding for configuration details.
Digital Delay Filter with PWMOFF Output
Bit 7 of the DDELAY register is the Programmable Comparator circuit enable (COMPEN) bit. If COMPEN=0, the Program-
mable Comparator circuit is disabled and the C
OUT
signal is low. If COMPEN=1, the Programmable Comparator circuit is
enabled and the C
OUT
signal is generated by the comparison of the two inputs.
Bit 6 (PWMINT) of the DDELAY register, if set to 1, selects the PWMOFF signal in place of its G6 input to the MIW circuit.
Software must then enable the MIW PWMOFF/G6 circuit by setting the WKEN[6] bit. The WKEDG[6] bit must also be
cleared to select the rising edge transitions on the PWMOFF signal as its WKPND[6] bit trigger. Software may monitor the
WKPND[6] flag or enable the MIW hardware interrupt (EDGEI) to help detect when the PWMOFF signal is triggered.
3
Bit 5 (EPWM) of the DDELAY register is the digital delay filter and PWMOFF signal enable bit. The EPWM bit is active low
so that on power-up (after a system reset) the digital delay filter circuit is automatically enabled once the Programmable
Comparator circuit is enabled. If the Programmable Comparator and PWM Timer 1 circuits are enabled, since the filter is
defaulted enabled, the PWMOFF signal may disable the PWM Timer 1 upon a comparator transition. If the digital delay filter
and PWMOFF circuit is not needed, software must set the EPWM bit to 1 disabling the filter before enabling the Programma-
ble Comparator to prevent unwanted disables of the PWM Timer 1 circuit or its outputs.
Bit 4 (OFFMODE) of the DDELAY register determines how the PWMOFF signal affects the PWM Timer 1 circuit. If OFF-
MODE=0 and the Timer 1 circuit is configured in an enabled PWM Mode, Timer 1 is automatically disabled forcing the PWM
T1HS1 and T1HS2 output signals to their resting (off) states with the rising edge of the PWMOFF signal. The T1C0 bit of the
T1CNTRL2 register is cleared, reinitializing the 12-bit TMR1 counter to 0x000. Software must re-enable the Timer 1 circuit to
reactivate the PWM output signals. If OFFMODE=1 and Timer 1 is configured in PWM Mode, the T1HS1 and T1HS2 output
signals are forced to their resting (off) state until the current PWM cycle completes. Once the PWM cycle completes, the
PWMOFF signal releases the T1HS1 and T1HS2 output signals and they resume with their normal operation even if the C
OUT
signal remains active (1). The next PWMOFF trigger will not occur until the next rising edge of C
OUT
.
Bits 3-0 (DD[3:0]) of the DDELAY register determine how long to delay the trigger of the PWMOFF signal once the rising
edge of C
OUT
has been detected. Once the digital delay counter is triggered, the delay count is compared against the value
stored in the DD[3:0] bits. Once the delay counter completes its DD[3:0] count, if C
OUT
remains high, the PWMOFF signal is
triggered. The digital delay counters increment at the device reference clock rate (F
RCLK2
).
4
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