參數(shù)資料
型號(hào): FQB95N03L
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: JFETs
英文描述: N-Channel Logic Level PWM Optimized Power MOSFET
中文描述: 75 A, 30 V, 0.008 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB
封裝: TO-263AB, 3 PIN
文件頁數(shù): 5/11頁
文件大?。?/td> 229K
代理商: FQB95N03L
2002 Fairchild Semiconductor Corporation
FQB95N03L Rev. B1
F
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Typical Characteristic
(Continued)
T
C
= 25°C unless otherwise noted
100
1000
0.1
1
10
30
4000
C
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
=
C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
=
C
GD
0
2
4
6
8
10
0
10
20
30
40
50
V
G
,
Q
g
, GATE CHARGE (nC)
I
D
= 14A
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 48A
V
DD
= 15V
0
50
100
150
200
250
0
10
20
30
40
50
S
R
GS
, GATE TO SOURCE RESISTANCE (
)
V
GS
= 4.5V, V
DD
= 15V, I
D
= 15A
t
d(OFF)
t
r
t
d(ON)
t
f
0
50
100
150
200
250
300
350
0
10
20
30
40
50
S
R
GS
, GATE TO SOURCE RESISTANCE (
)
t
d(OFF)
t
r
t
f
V
GS
= 10V, V
DD
= 15V, I
D
= 15A
t
d(ON)
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
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