參數(shù)資料
型號(hào)： EV4101
廠商： LSI Corporation
英文描述： 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）)
中文描述： 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令））
文件頁(yè)數(shù)： 48/68頁(yè)
文件大?。?/td> 545K
代理商： EV4101
48
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
7.2.2 Transaction B1: First Word of a Two-Word Burst Write
Clock Cycle 3 –
An idle cycle is generated on Clock Cycle 3, because
the address of the transaction is not on the same page. (The BBCC
Configuration Register determines the page size.) This idle cycle is
needed, because the target is driving TRDYN and DEVSELN HIGH
during Clock Cycle 3, as required by the PCI active deassertion protocol.
The target 3-states these signals at the rising edge of Clock Cycle 4. If
an idle cycle was not inserted, and the transaction was intended for a
different target, then contention may have occurred just after the rising
edge of Clock Cycle 4, as the old target 3-states its TRDYN, and another
target begins to drive TRDYN.
Clock Cycle 4 –
A write transaction begins. Note that writes are always
single word writes, each with their own address phase.
Clock Cycle 5 –
The target responds by asserting TRDYN. The target
also drives WBURSTN LOW, indicating that if multiple, same page writes
exist in the write buffer, then the EV4101 should give them priority and
perform the back-to-back writes.
Clock Cycle 6 –
Data B1 is transferred on the rising edge of Clock
Cycle 6. WBURSTN is sampled on the rising clock edge where TRDYN
is asserted.
7.2.3 Transaction B2: Second Word of a Two-Word Burst Write
Clock Cycle 6 –
Transaction B2 begins without an idle cycle (defined as
a cycle where both FRAMEN and IRDYN are HIGH). An idle cycle is not
required when the second write is from the same initiator and to the
same target. The EV4101 chip also calculates INPAGEN from the
address to support RAS-parking targets.
The second burst write is not guaranteed when WBURSTN is asserted.
It is merely a request that the EV4101 prioritize back-to-back writes over
instruction or data fetches.
Clock Cycle 7 –
Write data is driven, along with the appropriate byte
enables.
Clock Cycle 8 –
Data B2 is transferred on the rising edge of Clock
Cycle 8.
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