參數(shù)資料
型號： GE28F008B3BA70
廠商： INTEL CORP
元件分類： PROM
英文描述： 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46
封裝： VFBGA-46
文件頁數(shù)： 39/70頁
文件大?。?/td> 1215K
代理商： GE28F008B3BA70
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
44
Datasheet
Table 19. Write Operations—32-Mbit Density
#Sym
Parameter
Density
32 Mbit
Unit
Product
70 ns
90 ns
100 ns
110 ns
VCC
3.0 V – 3.6 V6
90
100
2.7 V – 3.6 V
70
90
100
110
Note
Min
W1
tPHWL /
tPHEL
RP# High Recovery to WE# (CE#)
Going Low
4,5
150
ns
W2
tELWL /
tWLEL
CE# (WE#) Setup to WE# (CE#)
Going Low
4,5
0
000
0
ns
W3
tWLWH
/
tELEH
WE# (CE#) Pulse Width
1,4,5
45
60
70
ns
W4
tDVWH/
tDVEH
Data Setup to WE# (CE#) Going High
2,4,5
40
50
60
ns
W5
tAVWH /
tAVEH
Address Setup to WE# (CE#) Going
High
2,4,5
50
60
607070
70
ns
W6
tWHEH/
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
4,5
0
000
0
ns
W7
tWHDX/
tEHDX
Data Hold Time from WE# (CE#)
High
2,4,5
0
000
0
ns
W8
tWHAX /
tEHAX
Address Hold Time from WE# (CE#)
High
2,4,5
0
000
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1,4,5
25
30
ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3,4,5
200
ns
W11
tQVVL
VPP Hold from Valid SRD
3,4
0
ns
W12
tBHWH/
tBHEH
WP# Setup to WE# (CE#) Going
High
3,4
0
000
0
ns
W13
tQVBL
WP# Hold from Valid SRD
3,4
0
ns
W14
tWHGL
WE# High to OE# Going Low
3,4
30
ns
NOTES:
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP =tWLWH =tELEH =tWLEH =tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH =tWHWL =tEHEL =tWHEL =tEHWL.
2. Refer to Table 25, “Bus Operations(1)” on page 52 for valid AIN or DIN.
3. Sampled, but not 100% tested.
4. See Figure 12, “AC Input/Output Reference Waveform” on page 47 for timing measurements and maximum allowable input
slew rate.
6. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
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