參數(shù)資料
型號(hào): GE28F008B3BA70
廠商: INTEL CORP
元件分類: PROM
英文描述: 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46
封裝: VFBGA-46
文件頁(yè)數(shù): 45/70頁(yè)
文件大小: 1215K
代理商: GE28F008B3BA70
Datasheet
5
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
Description
-001
Original version
-002
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 A to ±50 A
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
-003
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
-004
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 s typical and 20 s maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005
BGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
BGA package top side mark information added (Section 6)
-006
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
-007
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
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