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參數(shù)資料
| 型號： | GE28F008B3BA70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46 |
| 封裝： | VFBGA-46 |
| 文件頁數(shù)： | 47/70頁 |
| 文件大?。?/td> | 1215K |
| 代理商： | GE28F008B3BA70 |
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28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
51
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device must have a 0.1 F ceramic capacitor connected between each VCC and GND,
and between its VPP and GND. These high-frequency, inherently low-inductance capacitors must
be placed as close as possible to the package leads.
9.4
Power Consumption
Intel flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its
standby mode, where current consumption is even lower. The combination of these features can
minimize memory power consumption, and therefore, overall system power consumption.
9.4.1
Active Power
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for ICC current values. Active power is the largest contributor to
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
9.4.2
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to ICCS. The flash stays in this static state with outputs valid
until a new location is read.
9.4.3
Standby Power
With CE# at a logic-high level (VIH) and the device in read mode, the flash memory is in standby
mode, which disables much of the device circuitry, and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#
transitions to a logic-high level during Erase or Program operations, the device continues to
perform the operation and consume corresponding active power until the operation is completed.
System engineers must analyze the breakdown of standby time versus active time and quantify the
respective power consumption in each mode for their specific application. This approach provides
a more accurate measure of application-specific power and energy requirements.
9.4.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes,
RP# going low de-selects the memory and places the outputs in a high-impedance state. Recovery
from deep power-down requires a minimum time of tPHQV (See “AC Read Characteristics” on
During program or erase modes, RP# transitioning low aborts the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power
to the device clears the Status Register).
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