參數(shù)資料
型號(hào)： GE28F008B3BA70
廠商： INTEL CORP
元件分類： PROM
英文描述： 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46
封裝： VFBGA-46
文件頁(yè)數(shù)： 49/70頁(yè)
文件大?。?/td> 1215K
代理商： GE28F008B3BA70
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
53
10.1.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a
high-impedance state.
10.1.3
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during Program or Erase operation, the device continues to consume active power until
the Program or Erase operation is complete.
10.1.4
Deep Power-Down / Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-
impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required
until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read-array mode, and the Status Register is set to 80H. Figure 14, “Deep Power-
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process that takes time
tPLRH to complete.
2. After this time tPLRH, the part will either reset to read-array mode (if RP# has gone high during
enter reset mode (if RP# is still logic low after tPLRH, see Figure 14, “Deep Power-Down/
3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/
tPHEL must be waited before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than
when RP# goes high.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization can not occur because the
flash memory may be providing status information instead of array data. Intel
Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
10.1.5
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard microprocessor write timings to control Flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
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