參數(shù)資料
型號： GE28F008B3BA70
廠商： INTEL CORP
元件分類： PROM
英文描述： 1M X 8 FLASH 2.7V PROM, 70 ns, PBGA46
封裝： VFBGA-46
文件頁數(shù)： 57/70頁
文件大?。?/td> 1215K
代理商： GE28F008B3BA70
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
60
Datasheet
12.0
Block Locking
The B3 flash memory device architecture features two hardware-lockable parameter blocks.
12.1
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = VIL; any program or Erase operation to a locked
block will result in an error, which will be reflected in the Status Register:
For top configuration, the top two parameter blocks (blocks #133 and #134 for the 64 Mbit,
#69 and #70 for the 32 Mbit, blocks #37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8
Mbit, blocks #13 and #14 for the 4 Mbit) are lockable.
Table 29. Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
654
32
10
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine word program
or block-erase completion, before checking program or erase-
status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set at “1” until
an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted but failed to
program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered,
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK max and VPP1 min or between VPP1
max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Operation aborted
0 = No operation to locked blocks
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and must be masked out
when polling the Status Register.
NOTE:
A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.
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