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參數(shù)資料
| 型號(hào)： | GM76U256CLFW-12/E |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 120 ns, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | GM76U256CLFW-12/E |
GM76U256CL/LL
59
tWC
ADD
Write Cycle 2 (/CS Controlled) (Note 1, 2, 3)
tCW
VALID DATA
High-Z
tAW
tWR
tDH
tDW
/CS
/WE
DIN
DOUT
tAS
tWP
Notes:
1. The internal write time of the memory is defined by the overlap of /CS low and /WE low. Both signals
must be low to initiate a write and either signal can terminate a write by going high. The data input
set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
2. Data I/O is high impedance if /OE = VIH.
3. If /CS goes high simultaneously with /WE high, the output remains in a high impedance state.
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