參數(shù)資料
型號: HEF4017BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 5-stage Johnson decade counter
封裝: HEF4017BP<SOT38-4 (DIP16)|<<http://www.nxp.com/packages/SOT38-4.html<1<Always Pb-free,;HEF4017BT<SOT109-1 (SO16)|<<http://www.nxp.com/packages/SOT109-1.html<1<week
文件頁數(shù): 10/18頁
文件大小: 172K
代理商: HEF4017BP
HEF4017B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 14 September 2011
10 of 18
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Conditions: CP1 = LOW, while CP0 triggers on a LOW-to-HIGH transition, t
W
and t
rec
are measured when CP0 = HIGH and
CP1 triggers on a HIGH-to-LOW transition.
The shaded areas indicate where the output state is set by the input count.
Measurement points given in
Table 9
.
Fig 8.
Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
CP0 input
V
I
V
SS
V
I
V
SS
V
I
V
SS
V
OH
V
OL
V
OH
V
OL
Q1 - Q9
output
MR input
CP1 input
V
M
V
M
1/f
max
t
W
t
W
t
rec
V
M
1/f
max
t
W
t
PLH
t
PHL
V
M
V
M
001aaj306
Q0, Q5 - Q9
output
Hold times are shown as positive values, but may be specified as negative values;
Measurement points given in
Table 9
.
Fig 9.
Waveforms showing hold times for CP0 to CP1 and CP1 to CP0
001aae578
CP0 input
V
I
V
SS
V
I
V
SS
CP1 input
t
h
V
M
V
M
V
M
t
h
V
M
Table 9.
Supply voltage
V
DD
5 V to 15 V
Measurement points
Input
V
M
0.5V
DD
Output
V
M
0.5V
DD
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