參數(shù)資料
型號: HEF4024BP
廠商: NXP Semiconductors N.V.
元件分類: 通用總線功能
英文描述: 7-stage binary counter
封裝: HEF4024BP<SOT27-1 (DIP14)|<<http://www.nxp.com/packages/SOT27-1.html<1<Always Pb-free,;HEF4024BT<SOT108-1 (SO14)|<<http://www.nxp.com/packages/SOT108-1.html<1<week
文件頁數(shù): 6/14頁
文件大?。?/td> 100K
代理商: HEF4024BP
HEF4024B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 10 October 2011
6 of 14
NXP Semiconductors
HEF4024B
7-stage binary counter
[1]
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
t
is the same as t
TLH
and t
THL
.
[2]
t
t
transition time
see
Figure 5
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
[2]
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
-
-
-
60
30
20
80
35
25
20
15
15
5
13
18
60
30
20
30
15
10
40
20
15
10
5
5
10
25
35
120
60
40
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
t
W
pulse width
CP HIGH;
minimum width
see
Figure 5
MR HIGH;
minimum width
see
Figure 5
t
rec
recovery time
MR;
see
Figure 5
f
max
maximum
frequency
CP input;
J = K = HIGH;
see
Figure 5
Table 7.
V
SS
= 0 V; T
amb
= 25
C; for test circuit see
Figure 6
; unless otherwise specified.
Symbol Parameter
Conditions
Dynamic characteristics
…continued
V
DD
Extrapolation formula
[1]
Min
Typ
Max
Unit
Table 8.
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol
Parameter
V
DD
Typical formula for P
D
(
W)
P
D
dynamic power
dissipation
10 V
P
D
= 2100
f
i
+
(f
o
C
L
)
V
DD2
15 V
P
D
= 5200
f
i
+
(f
o
C
L
)
V
DD2
Dynamic power dissipation P
D
Where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
5 V
P
D
= 500
f
i
+
(f
o
C
L
)
V
DD2
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