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參數(shù)資料
| 型號(hào)： | HF88S05 |
| 廠商： | King Billion Electronics Co., Ltd. |
| 英文描述： | command mode SRAM device |
| 中文描述： | 命令模式SRAM器件 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 323K |
| 代理商： | HF88S05 |
of less significant 7 Bits of the internal shift register along with SDI pin will be transfer to SRAM at the
eighth rising edge of SCLK. The checksum register will be updated, and the TP register will be
incremented. The status of R_Wn, D_Cn and SDI must be held steady in the mean time.
KING BILLION ELECTRONICS CO., LTD
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股
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HF88S05
SRAM Series
December 18, 2003
This specification is subject to change without notice. Please contact sales person for the latest version before use.
9
V1.00
CS0_n
CS1
P_Sn
D_Cn
R_Wn
SDI
SCLK
TP
(TPP, TPH, TPL)
b7
020100
Series Data Write Mode
SDO
b1
b0
b7
b6
b6
b5
b4
b3
b2
b5
b7
b6
b4
b3
b2
b1
b0
020102
The bit 7 shall be shifted into register first.
020101
User shall update the initial address (TP) before
writing the data into SRAM.
7.4.
Serial Data Read Mode
If both R_Wn, and D_Cn are at high level at the eighth rising edge of SCLK then the contents of SRAM
been addressed will be latched into the internal shift register. Then the contents of shift register can be
shifted out with the next eight rising edges of SCLK.
So one thing important should be noted
here when using the Serial Data Interface to read SRAM data
is that one dummy read should be performed before the real data can be shifted out from SDO pin.
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