參數(shù)資料
型號(hào)： HFA3841
廠商： Intersil Corporation
英文描述： 288 MACROCELL 3.3 VOLT ISP CPLD
中文描述： 無(wú)線局域網(wǎng)媒體訪問(wèn)控制器
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 211K
代理商： HFA3841
21
SYNTHESIZER
For the PRISM II, the synthesizer is programmed by
firmware using different pins than the MMI. The HFA3841
will exchange data with the baseband during transmit and
receive operations over the MMI interface. If the MMI
interface was connected to the front end chips, the
transitions on SCLK and SD could couple noise into them.
The synthesizer serial bus consists of SYNTHDATA,
SYNTHCLK, LE_IF and LE_RF. SYNTHDATA is on pin PK2,
SYNTHCLK is on PK1, LE_IF is the enable for the HFA3783
Quad IF chip, and LE_RF is the enable for the HFA3683
synthesizer.
Data is provided on SYNTHDATA and clock on SYNTHCLK.
The data is updated the falling edge of SYNTHCLK and
expected to be latched into the synthesizer on the rising
edge. The enable signal LE_RF is asserted while data is
clocked out.
PHY Data Interface (MDI)
The HFA3841 has a dedicated serial port to provide the data
interface to the baseband processor. This is referred to as
the Modem Data Interface (MDI). The MDI operates on the
data being transferred to and from the baseband on a word
by word basis. There are no FIFOs needed, since the
firmware is able to control the protocol in real time.
The MDI performs the following functions:
Serial to parallel conversion of received data from the
baseband, with synchronization between the incoming RX
clock to the internal HFA3841 clock.
Generating CRCs (HEC and FCS) from the received data
stream to verify correct reception.
Decrypt the received data when WEP is enabled.
Parallel to serial conversion of transmit data, with the
serial timing synchronized with the TX clock.
Insertion of the CRCs (HEC and FCS) at the appropriate
point during transmission.
Encrypt the transmitted data when WEP is enabled.
The receive data path uses RX_RDY, RXC, RXD. The
transmit data path uses TX_RDY, TXC, TXD and the CCA
input to determine (under the IEEE802.11 protocol) whether
to transmit.
t
SCP
t
SCW
t
SCW
t
SCS
t
SCH
t
SCD
t
SCED
t
SCED
SCLK
SDI, R/W, SD, CS
SD (AS OUTPUT)
R/W
SD
FIGURE 18. BBP CONTROL PORT SIGNAL TIMING
TABLE 1. BBP CONTROL PORT AC ELECTRICAL
SPECIFICATIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
SCLK Clock Period
t
SCP
90
-
ns
SCLK Width Hi or Low
t
SCW
20
-
ns
Setup to SCLK + Edge
(SD, SDI, R/W, CS)
t
SCS
30
-
ns
Hold Time from SCLK +
Edge (SD, SDI, R/W, CS)
t
SCH
0
-
ns
SD Out Delay from SCLK +
Edge
t
SCD
-
30
ns
SD Out Enable/Disable
from R/W
t
SCED
-
15
ns
FIGURE 19. SYNTHESIZER DATA FORMAT
LE_RF
SYNTHCLK
SYNTHDATA
D23
D22
D21
D20
D1
D0
Preliminary - HFA3841
相關(guān)PDF資料
PDF描述
HFA3841CN 288 MACROCELL 3.3 VOLT ISP CPLD
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HFA3842A PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842AIN 3.3V 288-mc CPLD
HFA3842AIN-TK Circular Connector; No. of Contacts:41; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3841CN 制造商:Rochester Electronics LLC 功能描述:- Bulk
HFA3841CN96 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Medium Access Controller
HFA3842 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Medium Access Controller
HFA3842A 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
HFA3842AIN 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller
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