參數(shù)資料
型號(hào): HFA3841
廠商: Intersil Corporation
英文描述: 288 MACROCELL 3.3 VOLT ISP CPLD
中文描述: 無線局域網(wǎng)媒體訪問控制器
文件頁(yè)數(shù): 25/27頁(yè)
文件大?。?/td> 211K
代理商: HFA3841
25
PE1 and PE2 encoding details are found in Table 5.
Note that during normal receive and transmit operation that
PE1 is static and PE2 toggles for receive and transmit
states.
FIGURE 24. TRANSMIT CONTROL SIGNAL SEQUENCING
PE1
PE2
TR_SW
TR_SW_BAR
TX_PE
TX_RDY
PA_PE
t
D1
t
D2
t
D5
t
D3
t
D4
TABLE 4. TRANSMIT CONTROL TIMING SPECIFICATIONS
PARAMETER
SYMBOL
DELAY
TOLERANCE UNITS
PE2 to TR Switch
t
D1
2
±
0.1
μ
s
PE2 to BBP TX_PE
t
D2
TBD
±
0.1
μ
s
PE2 to PA_PE
t
D3
3
±
0.1
μ
s
PA_PE to PE2
t
D4
3
±
0.1
μ
s
TR Switch to PE2
t
D5
2
±
0.1
μ
s
TABLE 5. POWER ENABLE STATES
PE1
PE2
PLL_PE
Power Down State
0
0
1
Receive State
1
1
1
Transmit State
1
0
1
PLL Active State
0
1
1
PLL Disable State
X
X
0
NOTE: PLL_PE is controlled via the serial interface, and can be
used to disable the internal synthesizer, the actual synthesizer con-
trol is an AND function of PLL_PE, and a result of the OR function of
PE1 and PE2. PE1 and PE2 will directly control the power enable
functionality of the LO buffer(s)/phase shifter.
Preliminary - HFA3841
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