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參數(shù)資料
| 型號： | HFA3842AIN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | 1 CHANNEL(S), 11M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, PLASTIC, MS-026BHB, LQFP-128 |
| 文件頁數(shù)： | 18/27頁 |
| 文件大?。?/td> | 528K |
| 代理商： | HFA3842AIN |
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18
PHY BASEBAND PROCESSOR
The PHY baseband processor is programmed by HFA3842A
firmware.
The PRISM II baseband processor mode works as follows:
The Control Port consists of 3 signals: SD (serial data),
SCLK (serial clock), and CS_BAR (active-low chip select).
Control Port signaling for read and write operations is
illustrated in Figures 17 and 18 respectively. Detailed timing
relationships appear in Figure 19 and timing specifications
are contained in Table 7.
The BBP always uses the rising edge when clocking data on
the Control Port. This means that when the BBP is receiving
data it uses the rising edge of clock to sample; when driving
data, transitions occur on the rising edge.
Address bits 6 through 1 are significant for selecting
configuration registers. Address bits 7 and 0 are unused.
See the BBP Programming section for register addresses
and suggested values.
For read operations, the rising edge of R/W must occur after
the 7th but prior to the 8th rising edge of SCLK. This ensures
that the first data bit is clocked out of the BBP prior to the
edge used to clock it into the MAC.
For more detailed information on the Control Port and BBP
register programming see the HFA386x data sheets.
FIGURE 16. BLOCK DIAGRAM OF A BUFFER ACCESS PATH
BUFFER DESCRIPTOR
ACCESS (FIRMWARE)
ALLOCATE/
DEALLOCATE
REQUEST
BLOCK
OFFSET
VIRTUAL
FRAME BUFFER
DATA PORT
PRE-READ/
POST-WRITE
OFFSET CENTER
HOST
BUS
STATUS
HEADER
DATA
BUFFER
MEMORY
A
FID
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6 5
4
3
2
7
6
1
0
SCLK
FIRST DATABIT OUT
MSB
ADDRESS IN
DATA OUT
MSB
LSB
FIRST ADDRESS BIT
SD
R/W
CS
FIGURE 17. PRISM
II BASEBAND PROCESSOR CONTROL PORT READ TIMING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCLK
MSB
ADDRESS IN
MSB
DATA IN
LSB
SD
R/W
CS
FIGURE 18. PRISM II BASEBAND PROCESSOR SERIAL CONTROL PORT WRITE TIMING
HFA3842A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3842AIN-TK | Circular Connector; No. of Contacts:41; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-41 RoHS Compliant: No |
| HFA3860B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴頻基帶處理器) |
| HFA3860 | 3.3V 288-mc CPLD |
| HFA3860IV | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3860IV96 | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3842AIN-TK | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842BIN-TK | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PCMCIA/USB Wireless LAN Medium Access Controller |
| HFA3842IN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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