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參數(shù)資料
| 型號(hào)： | HFA3860 |
| 廠商： | Intersil Corporation |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | 11 Mbps的直接序列擴(kuò)頻基帶處理器 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 250K |
| 代理商： | HFA3860 |
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4-7
TX Port
The transmit data port accepts the data that needs to be
transmitted serially from an external data source. The data is
modulated and transmitted as soon as it is received from the
external data source. The serial data is input to the HFA3860
through TXD using the next rising edge of TXCLK to clock it in
the HFA3860. TXCLK is an output from the HFA3860. A
timing scenario of the transmit signal handshakes and
sequence is shown on timing diagram Figure 4.
The external processor initiates the transmit sequence by
asserting TX_PE. TX_PE envelopes the transmit data packet
onTXD.TheHFA3860respondsbygeneratingaPreambleand
Header. Before the last bit of the Header is sent, the HFA3860
begins generating TXCLK to input the serial data on TXD.
TXCLK will run until TX_PE goes back to its inactive state
indicating the end of the data packet. The user needs to hold
TX_PE high for as manyclocks as there bits to transmit.For the
higher data rates, this will be in multiples of the number of bits
per symbol. The HFA3860 will continue to output modulated
signal for 2
μ
s after the last data bit is output, to supply bits to
flush the modulation path. TX_PE must be held until the last
data bit is sampled. The minimum TX_PE inactive pulse
required to restart the preamble and header generation is
2.22
μ
s and to reset the modulator is 4.22
μ
s.
The HFA3860 internally generates the preamble and
header information from information supplied via the
control registers. The external source needs to provide only
the data portion of the packet and set the control registers.
The timing diagram of this process is illustrated on Figure
4. Assertion of TX_PE will initialize the generation of the
preamble and header. TX_RDY, which is an output from the
HFA3860, is used to indicate to the external processor that
the preamble has been generated and the device is ready
to receive the data packet (MPDU) to be transmitted from
the external processor. Signals TX_RDY, TX_PE and
TXCLK can be set individually, by programming
Configuration Register (CR) 1, as either active high or
active low signals.
The transmit port is completely independent from the
operation of the other interface ports including the RX port,
therefore supporting a full duplex mode.
CR18
Signal Field (BPSK - Mod. Walsh Sequence)
R/W
48
CR19
Signal Field (QPSK - Mod. Walsh Sequence)
R/W
4C
CR20
TX Signal Field
R/W
50
CR21
TX Service Field
R/W
54
CR22
TX Length Field (High)
R/W
58
CR23
TX Length Field (Low)
R/W
5C
CR24
RX Status
R
60
CR25
RX Service Field Status
R
64
CR26
RX Length Field Status (High)
R
68
CR27
RX Length Field Status (Low)
R
6C
CR28
Test Bus Address
R/W
70
CR29
Test Bus Monitor
R
74
CR30
Test Register 1, Must Load 00H
R/W
78
CR31
Test Register 2, Must Load 02H
R/W
7C
TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (Continued)
CONFIGURATION
REGISTER
NAME
TYPE
REGISTER
ADDRESS HEX
HFA3860
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3860IV | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3860IV96 | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861A | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| HFA3861B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
| HFA3861 | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴(kuò)頻基帶處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AEVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860AIV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
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