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參數(shù)資料
| 型號(hào)： | HFA3860B |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| 中文描述： | 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器） |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 330K |
| 代理商： | HFA3860B |
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2-26
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to
±
25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at
±
50ppm and the performance is shown in
Figure 18. This figure shows that the baseband processor in
the high rate modes is better than at low rates in tracking
clock offsets. The data for this figure and the next one was
taken with the SNR into the receiver set to achieve 1E
-5
BER
with no offset. Then the offset was varied to determine the
change in performance.
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for
demodulation in the 1 and 2Mbps modes are time invariant
matched filter correlators otherwise known as parallel
correlators. They use two samples per chip and are tapped
at every other shift register stage. Their performance with
carrier frequency offsets is determined by the phase roll rate
due to the offset. For an offset of +50ppm (combined for both
TX and RX) will cause the carrier to phase roll 22.5 degrees
over the length of the correlator. This causes a loss of
0.22dB in correlation magnitude which translates directly to
Eb/N0 performance loss. In the PRISM chip design, the
correlator is not included in the carrier phase locked loop
correction, so this loss occurs for both acquisition and data.
In the high rate modes, the data demodulation is done with a
set of correlators that are included in the carrier tracking
loop, so the loss is less. Figure 19 shows the loss versus
carrier offset taken out to +75ppm (120kHz is 50ppm at
2.4GHz).
FIGURE 18. BER vs CLOCK OFFSET
CLOCK OFFSET (PPM)
-50
-40
-30
-20
-10
0
10
20
30
40
50
BER 1.0
BER 2.0
BER 5.5
BER 11
1.00E
-04
1.00E
-05
1.00E
-06
FIGURE 19. BER vs CARRIER OFFSET
-50
-40
-30
CARRIER OFFSET AT 2.4GHz (PPM)
-20
-10
0
10
20
30
40
50
1.00E
-04
1.00E
-05
1.00E
-06
B
BER 1.0
BER 2.0
BER 5.5
BER 11
HFA3860B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3860 | 3.3V 288-mc CPLD |
| HFA3860IV | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3860IV96 | 11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861A | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器) |
| HFA3861B | Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)譜基帶處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860BIV | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
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