參數(shù)資料
型號： HFA3860B
廠商： Intersil Corporation
元件分類： 基帶處理器
英文描述： Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器)
中文描述： 直接序列擴(kuò)頻基帶處理器（直接序列擴(kuò)頻基帶處理器）
文件頁數(shù)： 32/40頁
文件大?。?/td> 330K
代理商： HFA3860B
2-32
Bit 4
SFD search status (set to 0 when RX_PE is inactive)
0 = Searching
1 = SFD Found
Bit 3
Signal Field Valid (set to 0 when RX_PE is inactive) signal field must be one of the 4 field values in CR 16 to CR19
0 = Not Valid
1 = Valid
Bit 2
Valid header CRC (set to 0 when RX_PE is inactive)
0 = Not Valid
1 = Valid
Bit 1
Antenna received on. Indicates antenna the receiver was on when last valid CRC check occurred.
0 = Antenna B
1 = Antenna A
Bit 0
Always 0
CONFIGURATION REGISTER 24 ADDRESS (60h) RX STATUS
This read only register is provided for MACs that can’t process the header fields from the RXD port.
CONFIGURATION REGISTER 25 ADDRESS (64h) RX SERVICE FIELD STATUS
Bits 7:0
This register contains the detected received 8-bit value of the Service Field for the Header. This field is reserved for future
use. It should be the value programmed into register 21 of the transmitter.
CONFIGURATION REGISTER 26 ADDRESS (68h) RX LENGTH FIELD STATUS (HIGH)
Bits 7:0
This register contains the detected higher byte (bits 8 - 15) of the received Length Field contained in the Header. This byte
combined with the lower byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX LENGTH FIELD STATUS (LOW)
Bits 7:0
This register contains the detected lower byte of the received Length Field contained in the Header. This byte combined with
the upper byte indicates the number of transmitted bits in the data packet.
CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS
Supplies address for test pin outputs and Test Bus Monitor Register
Bits 7:0
Test Bus Address = 00h
Quiet Test Bus
Test 7:0 = 00
TEST_CLK = 0
Bits 7:0
Test Bus Address = 01h
RX Acquisition Monitor
These bits sequentially go high as the signal is input. Transitions are aligned to chip boundaries.
Bits are reset after last chip of message.
Test 7 = A/DCal (Full Scale)
Test 6 = CRS, Carrier Sense
Test 5 = ED, energy detect comparator output
Test 4 = Track, indicates start of tracking and start of SFD time-out
Test 3 = SFD Detect, variable time after track start
Test 2 = Signal Field Ready, ~ 8
μ
s after SFD Detect
Test 1 = Length Field Ready, ~ 32
μ
s after SFD Detect
Test 0 = Header CRC Valid, ~ 48
μ
s after SFD Detect
TEST_CLK = Initial Detect
Bits 7:0
Test Bus Address = 02h
TX Field Monitor.
These bits sequentially go high as the signal is output. Transitions are aligned to chip boundaries. Bits are
reset after last chip of valid message.
Test 7 = A/DCal (Full Scale)
Test 6 = TXPE Internal, Inactive edge of pad TXPE delayed
Test 5 = Preamble Start
Test 4 = SFD Start
Test 3 = Signal Field Start
Test 2 = Length Field Start
Test 1 = Header CRC Start
Test 0 = MPDU Start
TEST_CLK = IQMARK, identifies symbol boundaries on IOUT and QOUT
HFA3860B
相關(guān)PDF資料
PDF描述
HFA3860 3.3V 288-mc CPLD
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HFA3861A Direct Sequence Spread Spectrum Baseband Processor(直接序列擴(kuò)頻基帶處理器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HFA3860BIV 制造商:Rochester Electronics LLC 功能描述:- Bulk
HFA3860BIV WAF 制造商:Harris Corporation 功能描述:
HFA3860BIV96 制造商:Rochester Electronics LLC 功能描述:- Bulk
HFA3860IV 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:
HFA3860IV WAF 制造商:Harris Corporation 功能描述:
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