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參數(shù)資料
| 型號： | HFA3861 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Direct Sequence Spread Spectrum (DSSS) baseband processor(直接序列擴頻基帶處理器) |
| 中文描述： | 直接序列擴頻（DSSS）基帶處理器（直接序列擴頻基帶處理器） |
| 文件頁數(shù)： | 23/35頁 |
| 文件大?。?/td> | 218K |
| 代理商： | HFA3861 |
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23
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE
Bit 7:4
Part Code
1 = HFA3861 series
Bit 3:0
Version Code
0 = 3861 base Version
CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
Bit 7
This control bit selects the phase of the receive carrier rotation sense
Logic 1 = Inverted rotation (CW), Invert Q in
Logic 0 = normal rotation (CCW)
Bit 6
This control bit selects the phase of the transmit carrier rotation sense
Logic 1 = Inverted rotation (CW), Invert Q out.
Logic 0 = normal rotation (CCW)
Bit 5
This control bit selects the phase of the transmit output clock (TXCLK) pin
Logic 1 = Inverted TXCLK
Logic 0 = NON-Inverted TXCLK
Bit 4
This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin
Logic 1 = TX_RDY Active 0
Logic 0 = TX_RDY Active 1
Bit 3
This control bit selects the active level of the transmit enable (TX_PE) input pin
Logic 1 = TX_PE Active 0
Logic 0 = TX_PE Active 1
Bit 2
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin.
Logic 1 = CCA Active 1
Logic 0 = CCA Active 0
Bit 1
This control bit selects the active level of the MD_RDY output pin.
Logic 1 = MD_RDY is Active 0
Logic 0 = MD_RDY is Active 1
Bit 0
This controls the phase of the RX_CLK output
Logic 1 = Invert Clk
Logic 0 = Non-Inverted Clk
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W I COVER CODE
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bits 0 - 7
I cover code, nominally 48h
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W Q COVER CODE
Bits 0 - 7
Q cover code, nominally 48h
CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH
Bits 0 - 7
This register contains the count for the Preamble length counter. Setup while TX_PE is low. For IEEE 802.11 use 80h. For
other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition
performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. These suggested values include a 2
symbol TX power amplifier ramp up. If you program 128 you get 130.
HFA3861
相關PDF資料 |
PDF描述 |
|---|---|
| HFA3861IV | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861IV96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925 | 2.4GHz - 2.5GHz 250mW Power Amplifier(2.4GHz - 2.5GHz 250mW 功率放大器) |
| HFA3926 | 2.0GHz - 2.7GHz 250mW Power Amplifier(2.0GHz - 2.7GHz 250mW 功率放大器) |
| HFA3926IA | 2.0GHz - 2.7GHz 250mW Power Amplifier |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3861A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861AIN96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processo |
| HFA3861B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband Processor |
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