參數(shù)資料
型號(hào): HFA3861IV
廠商: INTERSIL CORP
元件分類: 無繩電話/電話
英文描述: Direct Sequence Spread Spectrum Baseband Processor
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP64
封裝: 10 X 10 MM, PLASTIC, TQFP-64
文件頁數(shù): 28/35頁
文件大?。?/td> 218K
代理商: HFA3861IV
28
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6
RXRF flag
0 = normal
1 = disables threshold
Bits 5:0
AGC threshold (0-64 range)
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR
Bits 7:4
Mid sat attenuation (0-30 range)
Bits 3:0
low sat attenuation (0-15 range)
CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC MINIMUM SIGNAL ATTENUATION
Bits 7:0
AGC minimum signal attenuation (0-64 range), 2’s compliment
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR
Bits 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Carrier Sense 2 scale factor (0-4 range) (000000 - 100000)
CONFIGURATION REGISTER 31 ADDRESS (3Eh) MANUAL TX POWER CONTROL
Bits 7:1
7 bits to DAC input, -64 to 63 range
Bit 0
unused
CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
Bit 7
Selection bit for DAC input test mode 7
0 = Barker
1 = Low rate I/Q samples
Bit 6
force high rate mode
0 = normal
1 = force high rate mode
Bit 5
TX 44 clock enable
0 = Normal
1 = enabled
Bit 4
Tristate test bus and enable inputs
0 = Normal
1 = enable inputs on test bus
Bit 3
Disable spread sequence for 1 and 2Mbps
0 = Normal
1 = disabled
Bit 2
Disable scrambler
0 = normal scrambler operation
1 = scrambler disabled (taps set to 0)
Bit 1
PN generator enable (RX 44MHz clock)
0 = not enabled
1 = enabled
Bit 0
PN generator enable (RX 22MHz clock)
0 = not enabled
1 = enabled
HFA3861
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