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參數(shù)資料
| 型號： | HI-3583CJIF-10 |
| 廠商： | Holt Integrated Circuits |
| 英文描述： | 3.3V ARINC 429 TERMINAL IC |
| 中文描述： | 3.3終端芯片的ARINC 429 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HI-3583CJIF-10 |
v
DD
GND
GND
RIN1B
OR
RIN2B
RIN1A
OR
RIN2A
DIFFERENTIAL
AMPLIFIERS
ONES
COMPARATORS
NULL
ZEROES
v
DD
FIGURE 1. ARINC RECEIVER INPUT
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582/
HI-3583 data bus during data read or write operations. The
following table describes this mapping:
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
CR15=0
13
12
11
10
9
31
30
32
P
1
2
3
4
5
6
7
8
BYTE 1
ARINC
BIT
CR15=1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BYTE 2
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
CR15=0
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
ARINC
BIT
CR15=1
32
P
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
The HI-3582/HI-3583 guarantee recognition of these levels with a
common mode Voltage with respect to GND less than ±4V for the
worstcasecondition(3.0Vsupplyand13Vsignallevel).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls,thechiprejectsthedata.
1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register.
manner the minimum pulse width is guaranteed.
In this
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
HIGH SPEED
LOW SPEED
DATABIT RATE MIN
DATABIT RATE MAX
RECEIVER LOGICOPERATION
BIT TIMING
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
Figure2showsablockdiagramofthelogicsectionofeach receiver.
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 μsec
1.5 ± 0.5 μsec
5 μsec ± 5%
10 ± 5 μsec
10 ± 5 μsec
34.5 to 41.7 μsec
The HI-3582/HI-3583 accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
operation achieves this is described below:
HIGH SPEED
LOW SPEED
FUNCTIONAL DESCRIPTION (cont.)
THERECEIVERS
ARINCBUSINTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specificationrequiresthefollowingdetectionlevels:
ONE
NULL
ZERO
+6.5Volts to +13Volts
+2.5Volts to -2.5Volts
-6.5Volts to -13Volts
STATE
DIFFERENTIALVOLTAGE
HI-3582, HI-3583
S
S
L
L
S
S
L
L
L
L
L
L
L
L
L
L
L
L
L
L
HOLT INTEGRATED CIRCUITS
4
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| HI-3583CJTF | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:3.3V ARINC 429 TERMINAL IC |
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