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參數(shù)資料
| 型號： | HI-3583PQIF |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V ARINC 429 TERMINAL IC |
| 中文描述： | 2 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFP-52 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HI-3583PQIF |
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
CONTROL WORD TIMING
RECEIVER FIFO AND LABEL READ TIMING
TRANSMITTER FIFO AND LABEL WRITE TIMING
TRANSMISSION TIMING
LINE DRIVER OUTPUT TIMING
Pulse Width -
t
t
t
50
100
40
ns
ns
ns
Setup - DATA BUS Valid to
Hold -
CWSTR
HIGH
HIGH to DATA BUS Hi-Z
Delay - Start ARINC 32nd Bit to
LOW: High Speed
Low Speed
t
t
16
128
μs
μs
Delay -
Delay -
LOW to
HIGH to
LOW
HIGH
t
t
0
ns
ns
420
520
Setup - SEL to
Hold - SEL to
LOW
HIGH
t
t
10
10
ns
ns
Delay -
Delay -
LOW to DATA BUS Valid
HIGH to DATA BUS Hi-Z
t
t
235
80
ns
ns
Pulse Width -
LOW (Same ARINC Word)
LOW (Next ARINC Word)
EN
or
t
60
65
200
ns
ns
ns
Spacing -
Spacing -
HIGH to next
HIGH to next
EN
t
t
Pulse Width -
or
t
120
ns
Setup - DATA BUS Valid to
Hold -
HIGH to DATA BUS Hi-Z
PL
HIGH
t
t
190
70
ns
ns
Spacing -
or
t
LABEL
110
150
ns
ns
Spacing between Label Write pulses
t
Delay -
HIGH to TX/R LOW
t
240
ns
Delay -
HIGH to
low
560
ns
Spacing -
HIGH to ENTX HIGH
t
0
ns
Delay - 32nd ARINC Bit to TX/R HIGH
t
50
ns
Spacing - TX/R HIGH to ENTX LOW
t
0
ns
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0)
high to low
low to high
t
t
1.0
1.0
1.5
1.5
2.0
2.0
CWSTR
CWSTR
D/R
D/R
EN
EN
D/R
EN
EN
EN
EN
EN1
EN2
EN
EN
PL1
PL2
PL
PL1
PL2
PL2
PL2
CWSTR
CWSET
CWHLD
D/R
D/R
D/REN
END/R
SELEN
ENSEL
ENDATA
DATAEN
EN
ENEN
READEN
PL
DWSET
DWHLD
PL12
TX/R
PL2EN
DTX/R
ENTX/R
fx
rx
Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed
Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed
t
t
25
200
ENDAT
ENDAT
PL2
HFT
t
μs
μs
μs
μs
(Low Speed, control register CR13 = Logic 1)
high to low
low to high
t
t
5.0
5.0
10
10
15
15
μs
μs
HFT
fx
rx
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz 0.1% with 60/40 duty cycle
HI-3582, HI-3583
REPEATER OPERATION TIMING
Hold -
HIGH to
HIGH
t
0
ns
Delay - TX/R LOW to ENTX HIGH
t
0
ns
t
175
ns
± 1%
PL
EN
PLEN
TX/REN
MR
MASTER RESET PULSE WIDTH
ARINC DATA RATE AND BIT TIMING
Delay -
LOW to
LOW
t
0
ns
EN
PL
ENPL
HOLT INTEGRATED CIRCUITS
13
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