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V
DD
GND
GND
RIN1B
OR
RIN2B
RIN1A
OR
RIN2A
DIFFERENTIAL
AMPLIFIERS
ONES
COMPARATORS
NULL
ZEROES
V
DD
FIGURE 1. ARINC RECEIVER INPUT
FUNCTIONAL DESCRIPTION (cont.)
THERECEIVERS
ARINCBUSINTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specificationrequiresthefollowingdetectionlevels:
ONE
NULL
ZERO
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
STATE
DIFFERENTIAL VOLTAGE
HOLT INTEGRATED CIRCUITS
4
HI-3584
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3584
data bus during data read or write operations. The following table
describes this mapping:
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
CR15=0
13
12
11
10
9
31
30
32
P
1
2
3
4
5
6
7
8
BYTE 1
ARINC
BIT
CR15=1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BYTE 2
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
ARINC
BIT
CR15=0
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
ARINC
BIT
CR15=1
32
P
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S
S
L
L
S
S
L
L
L
L
L
L
L
L
L
L
L
L
L
L
The HI-3584 guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±4V for the worst case
condition(3.0Vsupplyand13Vsignallevel).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls,thechiprejectsthedata.
RECEIVER LOGICOPERATION
BIT TIMING
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
Figure2showsablockdiagramofthelogicsectionofeach receiver.
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 μsec
1.5 ± 0.5 μsec
5 μsec ± 5%
10 ± 5 μsec
10 ± 5 μsec
34.5 to 41.7 μsec
The HI-3584 accepts signals that meet these specifications and re-
jects signals outside the tolerances. The way the logic operation
achieves this is described below:
HIGH SPEED
LOW SPEED
3. Each data bit must follow its predecessor by not less than 8
samples and no more than 12 samples. In this manner the bit
rate is checked. With exactly 1MHz input clock frequency, the
acceptabledatabitratesareasfollows:
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. The Word Gap timer samples the Null shift register every 10
input clocks (80 for low speed) after the last data bit of a valid
reception.
If the Null is present, the Word Gap counter is
incremented. Acountof3willenablethenextreception.
HIGH SPEED
LOW SPEED
DATABIT RATE MIN
DATABIT RATE MAX
1. Keytotheperformanceofthetimingcheckinglogicisanac-
curate 1MHz clock source.
Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally,fordatabits,theOne or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
thelowerbitswithinthedatabittime. ForaNullinthewordgap,
three consecutive Nulls must be found in both the upper and
lowerbitsofthesamplingshift register. Inthismannerthemini-
mumpulsewidthisguaranteed.