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參數(shù)資料
| 型號： | HI-3584PQTF |
| 廠商： | HOLT INTEGRATED CIRCUITS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
| 中文描述： | 1 CHANNEL(S), 125K bps, SERIAL COMM CONTROLLER, PQFP52 |
| 封裝： | ROHS COMPLIANT, PLASTIC, QFP-52 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 327K |
| 代理商： | HI-3584PQTF |
CFIFO
SEL
EN
CONTROL
BIT
/
COR/W
32 TO 16 DRIVER
32 BIT SHIFT REGISTER
TO PINS
CONTROLBITS
CR0, CR14
CLOCK
CLOCK
CLK
CAND
SEND OF
PARITY
CHECK
BIT
DATA
BIT CLOCK
WORD GAP
WORD GAP
TIMER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
DERROR
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
FIGURE 2.
RECEIVER BLOCK DIAGRAM
LABEL /
DECODE
COMPARE
M16 x 8
32 X 32
FIFO
D/R
FF
CMUX
L
CBITS
HF
FUNCTIONAL DESCRIPTION (cont.)
0
X
0
X
LoadFIFO
1
No
0
X
Ignoredata
1
Yes
0
X
LoadFIFO
0
X
1
No
Ignoredata
0
X
1
Yes
LoadFIFO
1
Yes
1
No
Ignoredata
1
No
1
Yes
Ignoredata
1
No
1
No
Ignoredata
1
Yes
1
Yes
LoadFIFO
CR2(3) ARINCword CR6(9)
matches
label
ARINCword
bits9,10
match
CR7,8(10,11)
FIFO
RECEIVERPARITY
The receiver parity circuit counts Ones received, including the
paritybit. Iftheresultisodd,then"0"willappearinthe32ndbit.
RETRIEVINGDATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
tabledescribesthisoperation.
HOLT INTEGRATED CIRCUITS
5
HI-3584
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| HI-3584PQTF-10 | Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
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相關代理商/技術參數(shù) |
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| HI-3584PQTF-10 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:Enhanced ARINC 429 3.3V Serial Transmitter and Dual Receiver |
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| HI-3585PCIF | 制造商:Holt Integrated Circuits 功能描述:Silicon Gate CMOS Device 44-Pin QFN EP |
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