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HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS6110 Rev. F)
11/06
PIN CONFIGURATION
(Top View)
5
52 Pin Plastic Quad Flat Pack (PQFP)
See page 35 for 64-Pin LPCC Pin Configuration
5
5
4
4
4
4
4
4
4
4
4
4
S
39 - VDDA
38 -
37 - BUSB
36 - VDDB
35 -
34 - TXINHB
33 - RCVB
32 - FFEMPTY
31 - RF0 / RCVCMDA
30 - RF1 / RCVCMDB
29 -
28 - VALMESS
27 - ERROR
BUSA
BUSB
RFLAG
D
D
D
D
D
R
R
R
B
R
C
G
M
R/
- 1
- 2
D0 - 3
D1 - 4
D2 - 5
D3 - 6
D4 - 7
D5 - 8
D6 - 9
D7 - 10
D8 - 11
D9 - 12
D10 - 13
W
CS
HI-6110PQI
&
HI-6110PQT
GENERALDESCRIPTION
The HI-6110 is a CMOS integrated circuit implementing the
MIL-STD-1553 (1553) data communications protocol
between a host processor and a dual redundant 1553 data
bus. The single chip architecture has a digital section
containing all necessary logic and memory to process and
store the command and data words for one complete 1553
message. The analog section includes dual transceivers
coupled to the 1553 buses through external current mode
transformers. The device is available in an industry
standard64-pin9mmsquareLPCCpackage,makingitthe
smallest dual redundant 1553 interface product on the
market.
The HI-6110 may be configured as a Bus Controller (BC), a
Remote Terminal (RT), a Monitor Terminal (MT), or a
MonitorTerminalwithassignedRTaddress.16-bitregisters
store incoming and outgoing Command, Status and Data
words. Using two 32-word data FIFOs, the HI-6110 can
store the maximum number of 1553 words occurring in any
message. Formessageswithtransmitteddatawords,data
maybewritteninadvanceoron-the-fly. Receiveddatacan
beretrievedon-the-flyorallatonceaftertheValidMessage
flagisasserted.
BC message sequences are initiated by a rising edge on
the BCSTART input, or a 0 to 1 transition at the BCSTART
bit in the Control Register. All RT command responses are
automatically initiated after a valid Command Word is
received.
Each bus has a dedicated Manchester encoder and analog
transformer driver. Each driver dissipates less than 200
mWofon-chippowerat100%dutycycle.
Each bus receiver has a dedicated Manchester decoder. In
BC mode, a RCV signal indicates when valid 1553 words
are received.
In RT/MT modes, RCV indicates a valid
command received, while the 1553 command decoder
updates a Message register so the external controller can
identify command type and respond appropriately.
Guaranteed by design, the HI-6110 cannot generate
messagesexceeding660uS,thedurationofaCommandor
StatusWordplus32contiguousdatawords.
The external host controller reads and writes a simplified
register structure in the HI-6110 over a 16-bit parallel bus.
The system designer has flexibility over many aspects of
configuration.Controlandstatusmonitoringcanbedonein
hardware(byreading/writingcontrolpins)orinsoftware(by
reading/writingregisterbits).
APPLICATIONS
MIL-STD-1553 Terminals
Flight Control and Monitoring
ECCM Interfaces
Stores Management
Test Equipment
Sensor Interfaces
Instrumentation
FEATURES
Monolithic CMOS technology
3.3V operation
Exceptionally low power
On-chip message buffering
Selectable master clock frequency
Dual differential 1553 bus transceivers
Bus Controller / Remote Terminal /
Monitor Terminal operating modes
Compliant to MIL-STD-1553B Notice 2
and MIL-STD-1760 Stores Management
MIL-STD-1553 / MIL-STD-1760
BC / RT / MT Message Processor
HI-6110
November 2006