參數(shù)資料
型號(hào)： HI-6110
廠商： Holt Integrated Circuits
英文描述： MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
中文描述： 符合MIL - STD - 1553 /符合MIL - STD - 1760年/放射/噸消息處理器
文件頁數(shù)： 13/36頁
文件大?。?/td> 532K
代理商： HI-6110
HOLT INTEGRATED CIRCUITS
13
HI-6110 (REMOTE TERMINAL MODE)
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
TheControlRegistervaluespecifiesHI-6110operatingmode,
clock frequency and the bus enabled for transmit. It can also
be used to address registers for read/write operations, assert
master reset, as well as data word suppression when illegal
commanddetectionisimplemented.
CLReRA3
RA2
RA1
TRA
RTBCNoMR
MSB
LSB
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
1
No UREPTO
RA0
RETRB
X
X
0
REGISTER FORMATS (RT Mode)
MIL-STD-1553 Message Data Word 15:0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
TRANSMIT DATA FIFO (Write only) Write Address: X011
R
ESET TRANSMIT DATA
The Transmit Data FIFO is 32-words deep and holds MIL-
STD-1553 message data. The FIFO is cleared on Master
ResetorbyanywritetoregisteraddressX010.
AnydatawordtobetransmittedbytheRTmustbeloadedinto
the TRANSMIT DATA FIFO
preceding MIL-STD-1553 word. Words are transmitted in the
ordertheyareloaded.
the mid-parity bit for the
before
FIFO
Write Address: X010
BIT
15
14
NAME
-
REPTO
FUNCTION
Notused.
Controlsthetime-outwhichcausestheNoResponseError.
0
17 usecGap(equivalenttothe57usecmeasurementof5.2.1.7oftheRTValidationTestPlan)
1
131usecGap
13
IDWT
Inhibit Data Word Transmission. When “illegal command detection” is required, this feature alows
“command illegalization”.
When the IDWT bit is set, normal transmission of ordinary and mode data words is
suppressed for all transmit commands. NOTE: There will be no VALMESS or ERROR assertion for the affected
message. For normal response to the next command, t
Wordb
SelectsthefrequencyoftheHI-6110externalCLKinput:
CLKSEL
Value
0
24MHz
1
12MHz
Thisbitmustberesetto“0”
his bit must be reset before
Status
it0istransmitted.
10-7
RA3:0
Register Address for HI-6110 register and data read / write operations. The register address is defined by
the logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000
ensures thatonlytheinputpinsareusedforaddressingregisters.
Reset ERROR. If RERR is low, the ERROR output pin can only be reset by asserting MR, master reset. Writing
RERR high causes the ERROR output to be reset (rising edge). If the RERR is left high, the ERROR output
will automaticallyresetafter3to4microseconds. Fornormaloperation,thisbitissetto“1”.
Setting either TRAor TRB to "1" enables transmission on MIL-STD-1553 BUSAor BUS B. Setting both TRAand
TRB selects neither bus. The RT protocol engine connects to the selected, active bus. The 1553 receiver,
Manchester decoder and RCV output signal are still operational on the inactive bus. This is useful when the
remoteterminal receives a command on the inactive bus, indicated by RCV signal output. The RT must switch
activebusesto service the command. Valid words received on the inactive bus can be read without changing
activebusby reading the Bus A Word or Bus B Word register, but the terminal cannot respond as transmit is
disabled.
NOTE:theTXINHAandTXINHBinputpinscanoverridebusenablement.
6
RERR
5-4
TRB,TRA
3-2
RTMODE,
BCMODE
HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins,
allowingtheusertoselect1553operatingmodeundereitherhardwareorsoftwarecontrol:
RTMODE
BCMODE
1553OPERATINGMODE
0
0
BusMonitor(MT),withassignedRTaddress
0
1
BusController(BC)
1
0
RemoteTerminal(RT)
1
1
BusMonitor(MT),withoutassignedRTaddress
NotusedinRTmode.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affectedbyMasterReset.
that command’s
12
CLKSEL
11
Reserved
1
!0
-
MR
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Bus A/B Word 15:0
BUS
BUS B WORD REGISTER (Read only) Read Address: 1010
(Read only) Read Address: 1001
A WORD REGISTER
In RT mode, the Bus A Word register holds the last valid
MIL-STD-1553 word received on Bus A. The Bus B Word
register holds the last valid MIL-STD-1553 word received on
BusB.
相關(guān)PDF資料
PDF描述
HI-6110PQI MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PQIF MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PQM MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PQMF MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PQT MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HI-6110_10 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 MIL-STD-1553 / MIL-STD-1760
HI-6110PCI 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PCIF 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PCM 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
HI-6110PCMF 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:MIL-STD-1553 / MIL-STD-1760 BC / RT / MT Message Processor
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