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參數(shù)資料
| 型號(hào)： | HI3026A |
| 廠商： | Intersil Corporation |
| 英文描述： | 8-Bit, 140 MSPS, Flash A/D Converter(8位、采樣速率為140MSPS閃速存儲(chǔ)器A/D轉(zhuǎn)換器) |
| 中文描述： | 8位，140 MSPS的，閃光的A / D轉(zhuǎn)換器（8位，采樣速率為140MSPS閃速存儲(chǔ)器的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 206K |
| 代理商： | HI3026A |
4-1387
Operating Modes
The HI3026A has two types of operating modes which are selected with Pin 45 (SELECT).
DMUX Mode (See Application Circuits, Figures 18, 19, 20)
Set the SELECT pin to V
CC
for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is out-
put after being demultiplexed by this
1
/
2
frequency divided
clock. The
1
/
2
frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.
When using multiple HI3026A units in parallel in this mode,
differences in the start timing of the
1
/
2
frequency divided clock
may cause operation as shown in the figure below. As a
countermeasure, the HI3026A is equipped with a function
which resets the
1
/
2
frequency divided clock. When resetting
this clock, the RESET pulse must be input to the RESET pin.
See the Timing Charts for the RESET pulse input timing. The
A/D converter can operate at f
C
(Min) = 140 MSPS in this
mode.
Straight Mode (See Application Circuits, Figures 21, 22, 23)
Set the SELECT pin to GND for this mode. In this mode, data
output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
NOTE: Where
σ
(LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter, t
AJ
is:
V
t
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Test Circuits
(Continued)
SIGNAL
SOURCE
COMPARATOR
A > B
PULSE
COUNTER
SIGNAL
SOURCE
HI3026A
LATCH
+
1
/
8
LATCH
A
f
C
4
B
8
16 LSB
2V
P-P
SINE WAVE
-1kHz
V
IN
CLK
CLK
f
C
LOGIC
ALALYZER
V
IN
CLK
AMP
8
1024
SAMPLES
ECL
BUFFER
OSC1
φ
: VARIABLE
OSC2
100MHz
f
R
100MHz
HI3026A
V
RT
V
RM2
V
RB
129
128
127
126
125
(LSB)
V
t
σ
V
IN
CLK
V
IN
CLK
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
t
AJ
=
-------------
=
σ
/22
x 2
π
f
.
TABLE 2. OPERATING MODE TABLE
OPERATING
MODE
SELECT
MAXIMUM
CONVERSION RATE
DATA OUTPUT
CLOCK OUTPUT
DMUX Mode
V
CC
140 MSPS
Demultiplexed Output 70 Mbps
The input clock is
1
/
2
frequency
divided and output at 70MHz.
Straight Mode
GND
100 MSPS
Straight Output 100 Mbps
The input clock is inverted and
output at 100MHz.
HI3026A
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