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參數(shù)資料
| 型號： | HI5810KIJ |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | CMOS 10 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 中文描述： | 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 423K |
| 代理商： | HI5810KIJ |
6-1785
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 1.5MHz the track period is 2
μ
s.
A simplified analog input model is presented in Figure 14.
During tracking, the A/D input (V
IN
) typically appears as a
380pF capacitor being charged through a 420
internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external “zero
” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time
constants or 1.4
μ
s. The maximum source impedance
(R
SOURCE
Max) for a 2
μ
s acquisition time settling to within
0.5 LSB is 164
.
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
Reference Input
The reference input V
REF
+ should be driven from a low
impedance source and be well decoupled.
As shown in Figure 15, current spikes are generated on the
reference pin during each bit test of the successive approxi-
mation part of the conversion cycle as the charge balancing
capacitors are switched between V
REF
- and V
REF
+ (clock
periods 5 - 14). These current spikes must settle completely
during each bit test of the conversion to not degrade the
accuracy of the converter. Therefore V
REF
+ and V
REF
-
should be well bypassed. Reference input V
REF
- is normally
connected directly to the analog ground plane. If V
REF
- is
biased for nulling the converters offset it must be stable
during the conversion cycle.
The HI5810 is specified with a 4.608V reference, however, it
will operate with a reference down to 3V having a slight
degradation in performance.
Full Scale and Offset Adjustment
In many applications the accuracy of the HI5810 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
The V
REF
+ and V
REF
- pins reference the two ends of the
analog input range and may be used for offset and full scale
adjustments. In a typical system the V
REF
- might be returned
to a clean ground, and the offset adjustment done on an input
amplifier. V
REF
+ would then be adjusted to null out the full
scale error. When this is not possible, the V
REF
- input can be
adjusted to null the offset error, however, V
REF
- must be well
decoupled.
Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V
IN
).
Control Signal
The HI5810 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by t
D
data), the output is updated.
The DRDY (Data Ready) status output goes high (specified
by t
D1
DRDY) after the start of clock period 1, and returns
low (specified by t
D2
DRDY) after the start of clock period 2.
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
enables the four least significant bits (D0 - D3). t
EN
and t
DIS
specify the output enable and disable times.
If the output data is to be latched externally, either the trailing
edge of data ready or the next falling edge of the clock after
data ready goes high can be used.
When STRT input is used to initiate conversions, operation is
slightly different depending on whether an internal or
external clock is used.
Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least t
R
STRT) before clock
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.
A low signal applied to STRT (at least t
W
STRT wide) can
now initiate a new conversion. The STRT signal (after a
delay of (t
D
STRT)) causes the clock to restart.
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
R
SOURCE
V
IN
R
SW
≈
420
C
SAMPLE
≈
380pF
R
SOURCE (MAX)
=
-t
ACQ
C
SAMPLE
ln [2
-(N + 1)
]
- R
SW
FIGURE 14. ANALOG INPUT MODEL IN TRACK MODE
20mA
10mA
0mA
5V
0V
5V
0V
I
REF
+
CLK
DRDY
2
μ
s/DIV.
CONDITIONS: V
DD
= V
AA
+ = 5.0V, V
REF
+ = 4.608V,
V
IN
= 2.3V, CLK = 750kHz, T
A
= 25
o
C
FIGURE 15. TYPICAL REFERENCE INPUT CURRENT
HI5810
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