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參數(shù)資料
| 型號： | HIP6012CVZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Buck and Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller |
| 中文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO14 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 365K |
| 代理商： | HIP6012CVZ |
7
FN4324.2
December 27, 2004
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6012) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180
o
.
The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole
(~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not shown
in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the log-log
graph of Figure 8 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying the
modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
o
.
Include worst case component variations when determining
phase margin.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
FIGURE 7. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
-
+
REF
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6012
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
Z
FB
F
LC
L
O
2
π
C
O
--------------------------------------
=
F
ESR
2
π
ESR
C
O
(
)
--------------------------------------------
=
F
Z1
----------------------------------
=
F
Z2
R3
)
C3
-------------------------+
=
F
P1
2
π
R2
--------+
------------------------------------------------------
=
F
P2
=
----------------------------------
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
20LOG
(R2/R1)
CLOSED LOOP
GAIN
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
HIP6012
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