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參數(shù)資料
| 型號： | HS1-80C86RH-8 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Radiation Hardened 16-Bit CMOS Microprocessor |
| 中文描述： | 16-BIT, 5 MHz, MICROPROCESSOR, CDIP40 |
| 封裝： | SIDE BRAZED, METAL SEALED, CERAMIC, DIP-40 |
| 文件頁數(shù)： | 12/37頁 |
| 文件大?。?/td> | 239K |
| 代理商： | HS1-80C86RH-8 |
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867
Spec Number
518055
Specifications HS-80C86RH
TABLE 5. BURN-IN DELTA PARAMETERS (+25
o
C)
PARAMETER
SYMBOL
DELTA LIMITS
Standby Power Supply Current
IDDSB
±
100
μ
A
Output Leakage Current
IOZL, IOZH
±
2
μ
A
Input Leakage Current
IIH, IIL
±
200nA
Low Level Output Voltage
VOL
±
80mV
TTL High Level Output Voltage
VOH1
±
600mV
CMOS High Level Output Voltage
VOH2
±
150mV
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE
GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
TESTED FOR -Q
RECORDED
FOR -Q
TESTED FOR -8
RECORDED
FOR -8
Initial Test
100%/5004
1, 7, 9
1 (Note 2)
1, 7, 9
Interim Test 1
100%/5004
1, 7, 9,
1,
(Note 2)
1, 7, 9
PDA 1
100%/5004
1, 7,
1, 7
Interim Test 2
100%/5004
1, 7, 9,
1,
(Note 2)
N/A
PDA 2
100%/5004
1, 7,
N/A
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3 (Note 2)
N/A
Subgroup B6
Sample 5005
1, 7, 9
N/A
Group C
Sample 5005
N/A
N/A
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group D
Sample 5005
1, 7, 9
1, 7, 9
Group E, Subgroup 2
Sample 5005
1, 7, 9
1, 7, 9
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.
2. Table 5 parameters only.
Functional Description
Static Operation
All HS-80C86RH circuitry is of static design. Internal
registers, counters and latches are static and require no
refresh as with dynamic circuit design. This eliminates the
minimum operating frequency restriction placed on other
microprocessors. The CMOS HS-80C86RH can operate
from DC to 5MHz. The processor clock may be stopped in
either state (HIGH/LOW) and held there indefinitely. This
type of operation is especially useful for system debug or
power critical applications.
The HS-80C86RH can be single stepped using only the CPU
clock. This state can be maintained as long as is necessary.
Single step clock operation allows simple interface circuitry to
provide critical information for bringing up your system.
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide
extremely low power operation since HS-80C86RH power
dissipation is directly related to operating frequency. As the
system frequency is reduced, so is the operating power until,
ultimately, at a DC input frequency, the HS-80C86RH power
requirement is the standby current, (500
μ
A maximum).
Internal Architecture
The internal functions of the HS-80C86RH processor are
partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU functional diagram.
These units can interact directly but for the most part
perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided by
this unit serves to increase processor performance through
improved bus bandwidth utilization. Up to 6 bytes of the
instruction stream can be queued while waiting for decoding
and execution.
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