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參數資料
| 型號： | HS1-81C56RH |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | Radiation Hardened 256 x 8 CMOS RAM |
| 中文描述： | 256 X 8 MULTI-PORT SRAM, 250 ns, CDIP40 |
| 文件頁數： | 12/14頁 |
| 文件大?。?/td> | 86K |
| 代理商： | HS1-81C56RH |
12
HS-81C55RH, HS-81C56RH
The outputs of the HS-81C55/56RH are “glitch-free”
meaning that you can write a “1” to a bit position that was
previously “1” and the level at the output pin will not change.
Note also that the output latch is cleared when the port
enters the input mode. the output latch cannot be loaded by
writing to the port if the port is in theinput mode. The result is
that each time a port mode is changed from input to output,
the output pins will go low. When the HS-81C55/56RH is
RESET, the output latches are all cleared and all 3 ports
enter the input mode.
When in the ALT1 or ALT2 modes, the bits of Port C are
structured like the diagram above in the simple input or
output mode, respectively.
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
Figure 7 shows how the HS-81C55/56RH I/O ports might be
configured in a typical system.
Timer Section
The timer is a 14 bit down counter that counts the TIMER IN
pulses and provides either a square wave or pulse when
terminal count (TC) is reached.
The timer has the I/O address XXXXX100 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register. (See Figure 5).
To program the timer, the COUNT LENGTH REG is loaded
first, one byte at a time, by selecting the timer addresses.
Bits 0-13 of the high order count register will specify the
length of the next count and bits 14-15 of the high order
register will specify the timer output mode (see Figure 8).
The value loaded into the count length register can have any
value from 2H through 3FFH in Bits 0-13.
FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001
FIGURE 8. TIMER FORMAT
PORT A
PORT C
PORT B
OUTPUT
PORT A
A INTR (SIGNAL DATA RECEIVED)
A BF (SIGNALS DATA READY)
A STB (ACKNOWL. DATA RCV’D)
B STB (LOAD PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL)
B INTR (SIGNALS BUFFER
READY FOR READING)
INPUT
TO HS-80C85RH
RST INPUT
TO/FROM
PERIPHERAL
INTERFACE
TO INPUT PORT
(OPTIONAL)
TO HS-80C85RH
RST INPUT
M2
M1
T13
T12
T11
T10
T9
T8
7
6
5
4
3
2
1
0
T7
T6
T5
T4
T3
T2
T1
T0
7
6
5
4
3
2
1
0
TIMER
MODE
MSB OF
CNT LENGTH
LSB OF
CNT LENGTH
TABLE 1. PORT CONTROL ASSIGNMENT
PIN
ALT1
ALT2
ALT3
ALT4
PC0
Input Port
Output Port
A INTR (Port A Interrupt)
A INTR (Port A Interrupt)
PC1
Input Port
Output Port
A BF (Port A Buffer Full)
A BF (Port A Buffer Full)
PC2
Input Port
Output Port
A STB (Port A Strobe)
A STB (Port A Strobe)
PC3
Input Port
Output Port
Output Port
B INTR (Port B Interrupt)
PC4
Input Port
Output Port
Output Port
B BF (Port B Buffer Full)
PC5
Input Port
Output Port
Output Port
B STB (Port B Strobe)
Spec Number
518056
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| HS-81C55RH | Radiation Hardened 256 x 8 CMOS RAM |
| HS-81C56RH | Radiation Hardened 256 x 8 CMOS RAM |
| HS9-81C55RH | Radiation Hardened 256 x 8 CMOS RAM |
| HS9-81C56RH | Radiation Hardened 256 x 8 CMOS RAM |
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相關代理商/技術參數 |
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| HS1-81C56RH-8 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 256 x 8 CMOS RAM |
| HS1-81C56RH-Q | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened 256 x 8 CMOS RAM |
| HS1820A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| HS1820B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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