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參數(shù)資料
| 型號： | HS9-82C54RH-Q |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Radiation Hardened CMOS Programmable Interval Timer |
| 中文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, CDFP24 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 171K |
| 代理商： | HS9-82C54RH-Q |
957
HS-82C54RH
Functional Description
General
The HS-82C54RH is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The HS-82C54RH solves one of the most common prob-
lems in any microcomputer system, the generation of accu-
rate time delays under software control. Instead of setting up
timing loops in software, the programmer configures the
HS-82C54RH to match his requirements and programs one
of the counters for the desired delay. After the desired delay,
the HS-82C54RH will interrupt the CPU. Software overhead
is minimal and variable length delays can easily be
accommodated.
Some of the other timer functions common to micro-comput-
ers which can be implemented with the HS-82C54RH are:
Real time clock
Event counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to
interface the HS-82C54RH to the system bus (see Figure 5).
FIGURE 5. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTION
(8)
CONTROL
WORD
REGISTER
D7-D0
RD
WR
A0
A1
CS
I
COUNTER
1
COUNTER
0
COUNTER
2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
OUT 2
GATE 2
CLK 2
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus
and generates control signals for the other functional blocks
of the HS-82C54RH. A1 and A0 select one of the three
counters or the Control Word Register to be read from/
written into. A “l(fā)ow” on the RD input tells the HS-82C54RH
that the CPU is reading one of the counters. A “l(fā)ow” on the
WR input tells the HS-82C54RH that the CPU is writing
either a Control Word or an initial count. Both RD and WR
are qualified by CS; RD and WR are ignored unless the
HS-82C54RH has been selected by holding CS low.
Control Word Register
The Control Word Register (Figure 6) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the HS-82C54RH, the data is stored in the
Control Word Register and is interpreted as a Control Word
used to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
Counter 0, Counter 1, Counter 2
These three functional clocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a single counter is shown in Figure 7. The
counters are fully independent. Each Counter may operate
in a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
FIGURE 6. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
(8)
DATA
BUS
BUFFER
READ/
WRITE
LOGIC
CONTROL
WORD
REGISTER
D7-D0
RD
WR
A0
A1
CS
I
COUNTER
1
COUNTER
0
COUNTER
2
OUT 1
GATE 1
CLK 1
OUT 0
GATE 0
CLK 0
OUT 2
GATE 2
CLK 2
Spec Number
518059
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