參數(shù)資料
型號(hào)： M4A3-512/256-10FAC
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 9/62頁(yè)
文件大小： 0K
描述： IC CPLD ISP 4A 512MC 388FPBGA
標(biāo)準(zhǔn)包裝： 60
系列： ispMACH® 4A
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 512
輸入/輸出數(shù)： 256
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 388-BBGA
供應(yīng)商設(shè)備封裝： 388-FPBGA（23x23）
包裝： 托盤
ispMACH 4A Family
17
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and
flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable
product term is provided for each I/O cell. The feedback signal drives the input switch matrix.
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type
register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of
the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed”
data comparison, where the first data value is stored, and then the second data value is put on the I/O pin
and compared with the previous stored value.
Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells.
It powers up to a logic low.
Zero-Hold-Time Input Register
The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with
loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path
setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased,
the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs
for which data is loaded from sources which have low (or zero) minimum output propagation delays from
clock edges.
D/L
Q
Block CLK3
Block CLK2
Block CLK1
Block CLK0
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
17466G-017
17466G-018
Figure 10. I/O Cell for ispMACH 4A Devices with 2:1
Macrocell-I/O Cell Ratio
Figure 11. I/O Cell for ispMACH 4A Devices with 1:1
Macrocell-I/O Cell Ratio
To Input
Switch
Matrix
Individual
Output Enable
Product Term
From Output
Switch Matrix
Power-up reset
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