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參數(shù)資料
| 型號(hào)： | HV9606SP |
| 廠商： | SUPERTEX INC |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | HV9606 Current-Mode PWM Controller with Supervisor |
| 中文描述： | SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 565K |
| 代理商： | HV9606SP |
4 4/15/2002-R.L2
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com
HV9606
Absolute Maximum Ratings*
V Input Voltage
Supply Voltage, V
DD
Gate Drive Supply Voltage, VX2
Operating Ambient Temperature Range -40
°
C to +85
°
C
Storage Temperature Range
Power Dissipation @ 25
°
C, SSOP
Power Dissipation @ 25
°
C, Plastic DIP 750mW
*All voltages referenced to SGND and PGND pins.
-0.3V to +250V
-0.3V to +6V
-0.3 to +15V
-65
°
C to +150
°
C
750mW
Ordering Information
Package Options
20-Pin SSOP
HV9606SP
Dice
HV9606X
__________________________________________________________________________________________________________________
Pinout
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
H
VDD
START
STOP
Vin
REF
SS
SYNC
RT
SGND
PGND
STATUS
SENSE
FB
COMP
NI
CA
CB
VX2
GATE
CS
Pin Description
V
DD
–
This is the supply pin for the PWM Logic and Analog circuits.
When the input voltage to the V
IN
pin exceeds the start voltage the
input regulator seeks to regulate the voltage on the capacitor
connected to this pin to a nominal 2.9V. After the PWM has
started, the bootstrap supply will regulate this voltage to a nominal
3.3V or 5V. With V
IN
connected to PGND the circuit can be
powered via this pin in the voltage range of 2.9V to 5.5V with a
nominal 2.8V UVLO.
START
– The resistive divider from V
IN
sets the start-up regulator
start voltage.
STOP
– The resistive divider from V
IN
sets the start-up regulator
stop voltage. A low power sleep mode function may be
implemented by pulling this pin to SGND.
V
IN
–
This is the startup linear regulator input. It can accept DC
input voltages in the range of 15V to 250V. With START and
STOP programmed to more than 20V, the leakage current on this
pin is less than 6
μ
A at V
IN
= 20V.
VREF –
This pin provides a
!
1% tolerance reference voltage.
SS
– A capacitor connected to this pin determines the soft start
time. Soft start may be initiated by a low VX2 voltage or an over
current condition when supervisor circuit STATUS output is low.
During short duration input interruptions when the output voltage
does not decay below programmed limits, the supervisor circuit
inhibits soft start to permit rapid recovery of the system.
SYNC –
This I/O pin may be connected to the SYNC pin of other
HV9606 circuits and will cause the oscillators to lock to the highest
frequency oscillator. Synchronization to a master clock is possible
by means of an open collector or open drain logic gate or
optocoupler, provided the low duty cycle does not exceed 50%. If
synchronization is utilized then a pull up resistor to V
DD
is required
to overcome the effects of parasitic capacitance on the circuit
board. The value of the resistor required will depend on the
operating frequency and master clock duty cycle.
RT –
The resistor connected from this pin to SGND sets the
frequency of the internal oscillator by setting the charging current
for the internal timing capacitor. The PWM output frequency is one
half the oscillator frequency.
SGND –
Common connection for all Logic and Analog circuits.
PGND –
Common connection for Gate Driver circuit.
CS –
This is the current sense input. Under normal operation the
over current limit is triggered when the voltage on this pin exceeds
0.5V
REF
, however, current sensing is blanked during the first 85ns
on time of the MOSFET to prevent false triggering during the turn
on switching transition. The loop control operating peak current
sense may be set to any level below 0.5V
REF
.
GATE –
This push-pull CMOS output is designed to drive the gate
of an N-Channel power MOSFET.
VX2 –
This is the supply pin for the Gate Driver circuit and is
generated by the Charge Pump V
DD
voltage doubler circuit. It
should be bypassed to PGND with a capacitor, typically 0.1
μ
F.
CA and CB –
The charge pump circuit uses a capacitor (typically
0.01
μ
F) connected between these pins to generate the VX2
voltage.
NI –
High impedance non-inverting input of the error amplifier.
COMP –
The output of the error amplifier.
FB –
High impedance inverting input of the error amplifier.
SENSE –
This is the input pin to the supervisory circuit. On a
rising input voltage the circuit changes state at a nominal 0.85V
+ 0.075V. When the input voltage is decaying the circuit changes
state a nominal 0.85V
REF
– 0.075V.
STATUS
– This is the output of the supervisory circuit. When the
sense-input voltage is high, this output is pulled up to V
DD
by a
10
μ
A current source and the Soft Start function is disabled. When
the sense-input is low, this output is pulled low and it may be used
to directly control the reset of a microprocessor or it may be used
to drive an optocoupler or LED indicator.
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