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參數(shù)資料
| 型號(hào)： | I5062-ZD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB Flash Disk Controller |
| 中文描述： | U盤(pán)控制器 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | I5062-ZD |
i5062-ZD
Release date: 03/10/2005
2005 iCreate Technologies Corporation
This document contains preliminary information on product but not yet fully characterized.
iCreate Technologies Corporation reserves the right to change the specification in any manner without notice.
Page 2
C
reate
2. Pin Configuration and Definition
Pin configuration
(TOP VIEW)
32 PIN TSOP TYPE-I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDA
VSSA
FD7
FD6
FD5
FD4
VDD
OSCI
OSCO
FD3
FD2
FD1
FD0
VSS
FCLE
FALE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LED
VSS
FCE3
FCE2
FCE1
FCE0
VDDA
DPLS
DMNS
VDD
FWEN
FREN
VDD
VSSA
FRDY
PPU
i5062-ZD
W Y W W
E F Y M Z Z . P
C
r e a t e
Figure 1. Pin configuration
Pin definition
Pin Number
Name
IO Type
Function
USB (2 pins)
USB bus D+.
USB bus D-.
25
24
DPLS
DMNS
Analog
Analog
Clock (2 pins)
6MHz crystal input.
Clock Out 6MHz crystal output.
8
9
OSCI
OSCO
Clock In
Flash (17 pins)
Bi-directional data bus signals to NAND flash.
3, 4, 5, 6, 11,
12, 13, 14
FD7, FD6, FD5,
FD4, FD3, FD2,
FD1, FD0
FCE3, FCE2,
FCE1, FCE0
FCLE
FALE
FREN
FWEN
FRDY
IO4
30, 29, 28,
27
O2
Active-low chip enable signals to NAND flash.
15
16
20
21
18
O4
O4
O4
O4
Command latch enable (CLE) of NAND flash.
Address latch enable (ALE) of NAND flash.
Active-low read enable signal to NAND flash.
Active-low write enable signal to NAND flash.
Ready/Busy from NAND flash.
I, ST, PU
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